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參數(shù)資料
| 型號： | TDA4885 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費家電 |
| 英文描述： | 150 MHz video controller with I2C-bus |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PDIP32 |
| 封裝： | 0.400 INCH, PLASTIC, SOT-232-1, SDIP-32 |
| 文件頁數(shù)： | 16/56頁 |
| 文件大?。?/td> | 396K |
| 代理商： | TDA4885 |
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1997 Nov 25
16
Philips Semiconductors
Product specification
150 MHz video controller with I
2
C-bus
TDA4885
Crosstalk at signal outputs (channel 1: pin 30; channel 2: pin 25; channel 3: pin 20)
α
ct(tr)
transient crosstalk suppression input rise/fall time = 1 ns;
note 26
f = 50 MHz
f = 100 MHz
10
25
dB
α
ct(f)
crosstalk suppression by
frequency
25
10
30
20
dB
dB
Internal feedback reference voltage;
see Fig.15 and note 27
V
ref(n)
internal reference voltage for
negative feedback polarity
FFH; FPOL = 0
00H; FPOL = 0
FPOL = 1
3.8
5.6
0.6
4.0
5.8
0.7
4.2
6.1
0.8
V
V
V
V
ref(p)
fixed internal reference voltage
for positive feedback polarity
variation of V
ref(n)
and V
ref(p)
in
the temperature range
variation of V
ref(n)
and V
ref(p)
with supply voltage V
P
V
ref
/
T
T
amb
=
20 to +70
°
C
0
±
1.0
%
V
ref
/
V
P
7.6 V
≤
V
P
≤
8.8 V
0
±
1.0
%
External reference voltages (REF
1
: pin 32; REF
2
: pin 27; REF
3
: pin 22);
see Fig.16 and note 28
V
32, 27, 22
external reference voltage
(equal to internal reference
voltage with control bit
FPOL = 0 )
variation of V
32, 27, 22
in the
temperature range
variation of V
32, 27, 22
with
supply voltage V
P
output resistance
maximum sink current
maximum source current
FFH
00H
3.8
5.6
4.0
5.8
4.2
6.1
V
V
V
32, 27, 22
/
T
T
amb
=
20 to +70
°
C
0
±
1.0
%
V
32, 27, 22
/
V
P
7.6 V
≤
V
P
≤
8.8 V
0
±
1.0
%
R
32, 27, 22
I
32, 27, 22
I
32, 27, 22
90
330
400
280
μ
A
μ
A
Output clamping, feedback inputs (channel 1: pin 31; channel 2: pin 26; channel 3: pin 21)
I
31, 26, 21(max)
maximum input current
during output clamping;
V
11
> 3.5 V; V
31, 26, 21
= 0.5 V
PEDST = 0; V
11
> 3.5 V
PEDST = 1; V
11
> 3.5 V
500
100
60
nA
V
30, 25, 20rbl(min)
minimum reference black level
minimum pedestal black level
maximum reference black level PEDST = 0; V
11
> 3.5 V
maximum pedestal black level
black level variation at CRT
black level variation between
clamping pulses related to
nominal colour signal
width of clamping pulse
0.01
0.01
2.4
2.4
0
0.1
0.1
2.8
2.8
40
0.1
0.5
0.5
4
4
200
0.5
V
V
V
V
mV
%
V
30, 25, 20rbl(max)
PEDST = 1; V
11
> 3.5 V
note 29
line frequency 60 kHz;
10% duty cycle
V
bl(CRT)
V
bl(lf)
t
W11
measured at V
11
= 3 V;
see Fig.8
see Fig.8
1
μ
s
t
d11(clamp)l
delay between clamping input
at pin 11 (leading edge) and
start of internal output clamping
pulse
300
ns
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
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