參數(shù)資料
型號： TDA4885
廠商： NXP SEMICONDUCTORS
元件分類： 消費家電
英文描述： 150 MHz video controller with I2C-bus
中文描述： SPECIALTY CONSUMER CIRCUIT, PDIP32
封裝： 0.400 INCH, PLASTIC, SOT-232-1, SDIP-32
文件頁數(shù)： 11/56頁
文件大小： 396K
代理商： TDA4885
1997 Nov 25
11
Philips Semiconductors
Product specification
150 MHz video controller with I
2
C-bus
TDA4885
10 CHARACTERISTICS
All voltages and currents are measured in test circuit of Fig.19; all voltages are measured with respect to GND (pins 9,
28, 23 and 18); V
P
= V
P1, 2, 3
= 8 V (pins 7, 29, 24 and 19); T
amb
= 25
°
C; nominal input signals [0.7 V (peak-to-peak
value) at pins 6, 8 and 10]; nominal colour signals at signal outputs (pins 30, 25 and 20); reference black level (V
rbl
)
approximately 0.7 V; nominal settings for brightness and contrast; maximum settings for OSD contrast and gain; no
limiting of contrast (V
17
= 5 V); no OSD fast blanking (pin 1 connected to ground); no gain modulation (pins 12, 13
and 14 connected to ground); notes 1 to 3; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supply
V
P
I
P
V
P1, 2, 3
supply voltage (pin 7)
supply current (pin 7)
channel supply voltage
(pins 29, 24 and 19)
channel supply current
(pins 29, 24 and 19)
7.6
7.6
8.0
20
8.0
8.8
25
8.8
V
mA
V
note 4
I
P1, 2, 3
signal outputs (pins 30, 25
and 20) open-circuit;
V
rbl
= 0.7 V; note 5
signal outputs switched to
switch-off voltage; note 1
40
45
mA
V
PSO
supply voltage for signal switch
off (threshold at pin 7)
7.2
V
Clamping and blanking pulses (pins 5 and 11)
V
5
input clamping and vertical
blanking input signal
note 6
no blanking, no input
clamping
blanking, no input clamping
input clamping, no blanking
V
5
= 1 V; note 7
pin 5 grounded; note 7
V
5
=
0.1 V; note 7
note 6; see Fig.7
0.1
+1.2
V
1.6
3.5
1.5
80
250
0.2
60
200
2.6
V
P
0.05
30
100
75
V
V
μ
A
μ
A
μ
A
ns/V
I
5
input current
t
r/f5
rise/fall time for input clamping
pulse, disable for blanking
width of input clamping pulse
delay between leading edges
of vertical blanking input pulse
and internal blanking pulse
t
W5
t
dl5
0.6
270
μ
s
ns
V
11
< 0.8 V; input pulse with
50 ns/V; threshold for rising
input pulse V
5
= 1.4 V;
threshold after input clamping
pulse V
5
= 3 V; see Fig.7
V
11
< 0.8 V; input pulse with
50 ns/V; threshold V
5
= 1.4 V;
see Fig.7
note 8
no blanking, no output
clamping
blanking, no output clamping
blanking, output clamping
t
dt5
delay between trailing edges of
vertical blanking input pulse
and internal blanking pulse
output clamping and blanking
input signal
115
ns
V
11
0.1
+0.8
V
2.0
3.5
2.6
V
P
V
V
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