參數(shù)資料
型號(hào): TC86R4600
廠商: Toshiba Corporation
英文描述: 64 Bit RISC Microprocessor(64位精簡(jiǎn)指令集微處理器)
中文描述: 64位RISC微處理器(64位精簡(jiǎn)指令集微處理器)
文件頁(yè)數(shù): 15/30頁(yè)
文件大?。?/td> 267K
代理商: TC86R4600
TC86R4600 64-bit RISC Microprocessor
T O S H IB A A M E R IC A E L E C T R O N IC C O M P O N E N T S , IN C
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13
Table 5: Cache comparison between R4000PC and R4600
R4000PC
R4600
Cache Sizes
Cache Line Sizes
Cache Index
Cache Tag
Cache Organization
Data cache write policy
8KB Instruction cache, 8KB Data cache
software selectable between 16B and 32B
vAddr
12..0
pAddr
35..12
direct mapped
write-allocate and write-back
16KB Instruction cache, 16KB Data cache
fixed at 32B
same
same
2-way set associative
write-allocate or not based on TLB entry,
write-through or write-back based on TLB
entry
same, with FIFO to select the set to refill
Data cache miss
stall, output address, copy dirty data to write-
back buffer, refill cache, output write-back data
sub-block ordering
sequential
restart after all data received and written to
cache
restart after all data received and written to
cache
2-bit cache state
5-8 cycles
1 parity bit per 8 data bits
1 parity bit per 8 data bits
Data order for block reads
Data order for block writes
Instruction cache miss
restart
Data cache miss restart
same
same
same
restart on first doubleword, send subsequent
doublewords to response buffer
1-bit cache state
3-4 cycles
1 parity bit per 32 data bits
same
Instruction Tag
Cache miss overhead
Instruction cache parity
Data cache parity
Table 6: TLB comparison between R4000PC and R4600
R4000PC
R4600
Instruction virtual address
translation
ITLB miss
2-entry ITLB
same
1 cycle penalty, refilled from JTLB, LRU
replacement
1 cycle on branch, jump, and
ERET
, 2 cycles
otherwise, refilled from JTLB, LRU replace-
ment
4-entry DTLB
Data virtual address transla-
tion
DTLB miss
done directly in JTLB
n.a.
1 cycle penalty, refilled from JTLB, pseudo-
LRU replacement
same
JTLB
48 entries of even/odd page pairs, fully
associative
4KB, 16KB, ..., 16MB
sets
TS
in
Status
and disables TLB until
Reset to prevent damage
VSIZE = 40
PSIZE = 36
Page size
Multiple entry match in JTLB
same
no damage for multiple match; no detection or
shutdown implemented
same
same
Virtual address size
Physical address size
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