參數(shù)資料
型號(hào): TC86R4600
廠商: Toshiba Corporation
英文描述: 64 Bit RISC Microprocessor(64位精簡(jiǎn)指令集微處理器)
中文描述: 64位RISC微處理器(64位精簡(jiǎn)指令集微處理器)
文件頁(yè)數(shù): 14/30頁(yè)
文件大?。?/td> 267K
代理商: TC86R4600
TC86R4600 64-bit RISC Microprocessor
12
T O S H IB A A M E R IC A E L E C T R O N IC C O M P O N E N T S , IN C
.
Tables 4 to 10 highlight some of the differences between the R4600 and the R4000PC.
Table 4: System interface comparison between R4000PC and R4600
R4000PC
R4600
I/O
Package
JTAG
Block transfer sizes
SClock divisor
Non-block writes
LVCMOS (3.3V
±
0.3V)
179-pin ceramic PGA
yes
16B or 32B
2, 3, 4, 6, or 8
max throughput of 4 SClock cycles
R46003: LVCMOS (3.3V
±
0.3V)
same and 208-pin CQFP (ceramic QFP)
no
32B
2, 3, 4, 6, or 8
two new system interface protocol options
that support 2 SClock cycle throughput
(remains 4 in compatibility mode)
different, as described in Table 3
bits
19..12
of virtual address
Serial configuration
Address bits
63..56
on
reads and writes
Uncached and write-
through stores
SysADC
SysADC for non-data cycles
Parity error during writeback
Error bit in data identifier of
read responses
Parity error on read data
as described in R4000 User’s Guide
zero
uncached stores stall until sent on system
interface
parity only
zero on R4000, parity on R4400
use Cache Error exception
Bus Error if error bit set for any doubleword
uncached and write-though stores buffered
in 4-entry write buffer
same
zero
output bad parity
Only check error bit of first doubleword; all
other error bits ignored
bad parity written to cache; take Cache Error
exception if bad parity occurs on double-
words that the processor is waiting for
0 cycles between address and data
0 latency
data bus maintains last D cycle value
Bus Error if parity error in any doubleword
Block writes
Release after Read Request
SysAD value for x cycles of
writeback data pattern
SysAD bus use after last D
cycle of writeback
Output slew rate
1-2 null cycles between address and data
variable latency
data bus undefined
unused for trailing x cycles (e.g. DDxxDDxx,
not DDxxDDxx)
simple CMOS output buffers with 2-bit static
strength control
driven high, do not connect
(reserved for future output)
should be corrected to high
(reserved for future input)
same
(reserved for future output)
same
(reserved for future input)
driven high, do not connect
(reserved for future output)
dynamic feedback control
IOOut
output
output slew rate control feedback loop output
IOIn
input
output slew rate control input
GrpRunB
output
do not connect
GrpStallB
input
should be connected to
VCC
FaultB
output pin
indicates compare mismatch
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