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參數(shù)資料
| 型號： | TC86R4600 |
| 廠商： | Toshiba Corporation |
| 英文描述： | 64 Bit RISC Microprocessor(64位精簡指令集微處理器) |
| 中文描述： | 64位RISC微處理器（64位精簡指令集微處理器） |
| 文件頁數(shù)： | 12/30頁 |
| 文件大?。?/td> | 267K |
| 代理商： | TC86R4600 |
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TC86R4600 64-bit RISC Microprocessor
10
T O S H IB A A M E R IC A E L E C T R O N IC C O M P O N E N T S , IN C
.
Differences from the R4000PC
The interface between R4600 and external logic is a subset of the
R4000PC interface, with two extensions for increased non-block
write bandwidth. Interface logic meets or exceeds the JEDEC
Standard for low-voltage CMOS-compatible (LVCMOS) VLSI
digital circuits. Compatibility with the LVBO and perhaps
LVTTL standards is desirable, but uncertain at this time.
The input clock for R4600 is multiplied by 2 by an on-chip
PLL to produce the internal clock. R4600 will generate output
clocks and operate its system interface at 1/2, 1/3, 1/4, 1/6, and
1/8 the frequency of the internal clock. For example, the R4600 at
its 100MHz internal execute rate requires a 50MHz input clock,
and supports either 50MHz, 33 MHz, 25 MHz, 16 MHz, or 12
MHz system interfaces. The input clock must be constant
frequency for PLL operation. The PLL is expected to operate
at frequencies from one fourth the maximum frequency to the
maximum frequency.
The differences between the R4000PC and R4600 are as
follows:
￥ Because the primary cache line is fixed at 32 bytes, only 32
byte block transfers will be supported.
￥ R4600 will not support JTAG.
￥ The R4600 serial configuration data stream will not be
R4000PC compatible; different values for the bit stream will
be required. The configuration protocol will remain the same.
There will be approximately 20 configuration node bits for
customers to control, located at the head of the configuration
stream. There will be additional bits for debugging purposes
that customers must set to zero.
￥ For graphics performance, R4600 will support two new inter-
face protocols to double the non-block write bandwidth of the
part. The new protocols will be enabled by two new mode bits;
the default is to remain compatible with existing R4000PC sys-
tems. The use of these options will double peak output power
consumption.
￥ The R4000 has feedback-controlled dynamic slew rate control
output drivers. R4600 will use simple CMOS output drivers.
Non-block write enhancements
The R4000PC interface protocol requires that
WrRdyB
be
asserted two system cycles prior to the issue of a write. An exter-
nal agent that deasserts
WrRdyB
immediately upon receiving the
write that Tlls its buffer therefore stops a write that would start
four system cycles after the Trst. The R4000 leaves two null sys-
tem cycles after a write address/data pair to give the external
agent time to stop its next write. This situation is illustrated in the
following Tgure:
Figure 10. R4000 PC Compatible Nonblock Write Protocol
SysClk
SysAD
Adr0
Data0
Adr1
Data1
SysCmd
WrRdyB
Write
NEOD
Write
NEOD
Issue
NoIss
NoIss
NoIss
Issue
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