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參數(shù)資料
| 型號(hào)： | TC1130 |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | 32-Bit Single-Chip Microcontroller |
| 中文描述： | 32位單片機(jī) |
| 文件頁(yè)數(shù)： | 70/113頁(yè) |
| 文件大?。?/td> | 1505K |
| 代理商： | TC1130 |
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TC1130
Data Sheet
66
V0.3, 2003-09
Clock Generation Unit
The Clock Generation Unit (CGU) allows a very flexible clock generation for TC1130.
The power consumption is indirect proportional to the frequency, whereas the
performance of the microcontroller is direct proportional to the frequency. During user
program execution the frequency can be programmed for an optimal ratio between
performance and power consumption. Therefore the power consumption can be
adapted to the actual application state.
Features
The Clock Generation Unit serves different purposes:
PLL Feature for multiplying clock source by different factors
Direct Drive for direct clock put through
Comfortable state machine for secure switching between basic PLL, direct or
prescaler operation
Power Down Mode support
USB Clock source and control
The Clock Generation Unit in the TC1130, shown in
Figure 19
, consists of an oscillator
circuit and one Phase-Locked Loop (PLL). The PLL can convert a low-frequency
external clock signal to a high-speed internal clock for maximum performance. The PLL
also has fail-safe logic that detects degenerate external clock behavior such as abnormal
frequency deviations or a total loss of the external clock. It can execute emergency
actions if it losses the lock on the external clock.
In general, the Clock Generation Unit (CGU) is controlled through the System Control
Unit (SCU) module of the TC1130.
Figure 19
Clock Generation Unit Block Diagram
1
>
MCA04940mod
Oscillator
Circuit
XTAL1
XTAL2
f
OSC
Phase
Detect.
VCO
N
Divider
PLL
f
VCO
1
MUX
0
1:1/1:2
Divider
f
SYS
Lock
Detector
OSCR
PLL_
LOCK
NDIV
[6:0]
VCO_
BYPASS
KDIV
[3:0]
PLL_
BYPASS
System Control Unit
SCU
Register PLL_CLC
MUX
K:1/K:2
Divider
VCO_
SEL[1:0]
f
CPU
SYS
FSL
Clock Generation Unit
CGU
P
Divi-
der
Osc.
Run
Detect.
PDIV
[2:0]
OSC
DISC
P4.0/
USBCLK
Divider
MUX
f
USB
Register SCU_CON
USBC
LDIV
USBC
LSEL
Register OSC_CON
MOSC
OGC
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