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參數(shù)資料
| 型號(hào)： | TC1130 |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | 32-Bit Single-Chip Microcontroller |
| 中文描述： | 32位單片機(jī) |
| 文件頁數(shù)： | 53/113頁 |
| 文件大?。?/td> | 1505K |
| 代理商： | TC1130 |
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TC1130
Data Sheet
49
V0.3, 2003-09
memory ranges from unauthorized read, write, or instruction fetch accesses. The
TriCore architecture provides up to four protection register sets with the PSW.PRS field
controlling the selection of the protection register set. Because the TC1130 uses a
Harvard-style memory architecture, each Memory Protection Register Set is broken
down into a Data Protection Register Set and a Code Protection Register Set. Each Data
Protection Register Set can specify up to four address ranges to receive particular
protection modes. Each Code Protection Register Set can specify up to two address
ranges to receive particular protection modes.
Each of the Data Protection Register Sets and Code Protection Register Sets
determines the range and protection modes for a separate memory area. Each contains
register pairs which determine the address range (the Data Segment Protection
Registers and Code Segment Protection Registers) and one register (Data Protection
Mode Register) which determines the memory access modes which apply to the
specified range.
Protection for PTE based translation
Memory protection for addresses that undergo PTE based translation is enforced using
the PTE used for the address translation. The PTE provides support for protecting a
process from unauthorized read, write, or instruction fetches by other processes. The
PTE has the following bits that are provided for the purpose of protection:
l XE (Execute Enable) enables instruction fetch to the page.
l WE (Write Enable) enables data writes to the page.
l RE (Read Enable) enables data reads from the page.
Furthermore, User-0 accesses to virtual addresses in the upper half of the virtual
address space are disallowed when operating in Virtual mode. In Physical mode, User-
0 accesses are disallowed only to segments 14 and 15. Any User-0 access to a virtual
address that is restricted to User-1 or Super-visor mode will cause a Virtual Address
Protection (VAP) Trap in both the Physical and Virtual modes.
Memory Checker
The Memory Checker Module (MCHK) allows to check the data consistency of
memories. It uses DMA moves to read from the selected address area and to write the
value read in a memory checker input register (the moves should be 32 bit moves). A
polynomial checksum calculation is done with each write operation to the memory
checker input register
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