參數(shù)資料
型號(hào)： TC1130
廠商： INFINEON TECHNOLOGIES AG
英文描述： 32-Bit Single-Chip Microcontroller
中文描述： 32位單片機(jī)
文件頁數(shù)： 19/113頁
文件大小： 1505K
代理商： TC1130
TC1130
Data Sheet
15
V0.3, 2003-09
TRST
T11
I
PDC
JTAG Module Reset/Enable Input
A low level at this pin resets and disables the JTAG
module. A high level enables the JTAG module.
JTAG Module Clock Input
JTAG Module Serial Data Input
JTAG Module Serial Data Output
JTAG Module State Machine Control Input
Trace Clock for OCDS_L2 Lines
Hardware Configuration Inputs
The Configuration Inputs define the boot options of the
TC1130 after a hardware invoked reset operation.
OCDS Break Input
A low level on this pin causes a break in the chip’s
execution when the OCDS is enabled. In addition, the
level of this pin during power-on reset determines the
boot configuration.
Ethernet Controller Transmit Clock
MII_TXD[3:0] and MII_TXEN are driven off the rising
edge of the MII_TXCLK by the core and sampled by
the PHY on the rising edge of the MII_TXCLK.
Ethernet Controller Receive Clock
MII_RXCLK is a continuous clock. Its frequency is 25
MHz for 100 Mbps operation, and 2.5 MHz for 10Mbps.
MII_RXD[3:0], MII_RXDV and MII_EXER are driven
by the PHY off the falling edge of MII_RXCLK and
sampled on the rising edge of MII_RXCLK.
Ethernet Controller Management Data Input /
Output
When a read command is being executed, data which
is clocked out of the PHY will be presented on the input
line. When the Core is clocking control or data onto the
MII_MDIO line, the signal will carry the information.
USB D+ data line
USB D- data line
TCK
TDI
TDO
TMS
TRCLK
HWCFG0
HWCFG1
HWCFG2
BRKIN
T12
T13
T10
T9
T8
M14
L14
T6
T5
I
I
O
I
O
I
I
I
I
PUC
PUC
PUC
PUC
PUC
PDC
PUC
MII_
TXCLK
T2
I
PDC
MII_
RXCLK
R2
I
PDC
MII_
MDIO
R1
I/O
PDA
D+
D-
T14
T15
I/O
I/O
Table 1
Pin Definitions and Functions
(cont’d)
Symbol
Pin
In
Out
PU/
PD
1)
Functions
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