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參數(shù)資料
| 型號(hào)： | TB28F008SA-100 |
| 廠商： | INTEL CORP |
| 元件分類： | DRAM |
| 英文描述： | 8-MBIT (1-MBIT x 8) FlashFileTM MEMORY |
| 中文描述： | 1M X 8 FLASH 12V PROM, 100 ns, PDSO44 |
| 封裝： | 0.525 X 1.110 INCH, PLASTIC, SOP-44 |
| 文件頁(yè)數(shù)： | 12/33頁(yè) |
| 文件大?。?/td> | 466K |
| 代理商： | TB28F008SA-100 |
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28F008SA
Write
Writes to the Command User Interface enable read-
ing of device data and Intelligent Identifiers. They
also control inspection and clearing of the Status
Register. Additionally, when V
PP
e
V
PPH
, the Com-
mand User Interface controls block erasure and byte
write. The contents of the interface register serve as
input to the internal state machine.
The Command User Interface itself does not occupy
an addressable memory location. The interface reg-
ister is a latch used to store the command and ad-
dress and data information needed to execute the
command. Erase Setup and Erase Confirm com-
mands require both appropriate command data and
an address within the block to be erased. The Byte
Write Setup command requires both appropriate
command data and the address of the location to be
written, while the Byte Write command consists of
the data to be written and the address of the loca-
tion to be written.
The Command User Interface is written by bringing
WE
Y
to a logic-low level (V
IL
) while CE
Y
is low.
Addresses and data are latched on the rising edge
of WE
Y
. Standard microprocessor write timings are
used.
Refer to AC Write Characteristics and the AC Wave-
forms for Write Operations, Figure 11, for specific
timing parameters.
COMMAND DEFINITIONS
When V
PPL
is applied to the V
PP
pin, read opera-
tions from the Status Register, intelligent identifiers,
or array blocks are enabled. Placing V
PPH
on V
PP
enables successful byte write and block erase oper-
ations as well.
Device operations are selected by writing specific
commands into the Command User Interface. Table
3 defines the 28F008SA commands.
Read Array Command
Upon initial device powerup and after exit from deep
powerdown mode, the 28F008SA defaults to Read
Array mode. This operation is also initiated by writing
FFH into the Command User Interface. Microproces-
sor read cycles retrieve array data. The device re-
mains enabled for reads until the Command User
Interface contents are altered. Once the internal
Write State Machine has started a block erase or
byte write operation, the device will not recognize
the Read Array command, until the WSM has com-
pleted its operation. The Read Array command is
functional when V
PP
e
V
PPL
or V
PPH
.
Table 4. Status Register Definitions
WSMS
ESS
ES
BWS
VPPS
R
R
R
7
6
5
4
3
2
1
0
SR.7
e
WRITE STATE MACHINE STATUS
1
e
Ready
0
e
Busy
SR.6
e
ERASE SUSPEND STATUS
1
e
Erase Suspended
0
e
Erase in Progress/Completed
SR.5
e
ERASE STATUS
1
e
Error in Block Erasure
0
e
Successful Block Erase
SR.4
e
BYTE WRITE STATUS
1
e
Error in Byte Write
0
e
Successful Byte Write
SR.3
e
V
PP
STATUS
1
e
V
PP
Low Detect; Operation Abort
0
e
V
PP
OK
SR.2–SR.0
e
RESERVED FOR FUTURE
ENHANCEMENTS
These bits are reserved for future use and
should be masked out when polling the Status
Register.
NOTES:
RY/BY
Y
or the Write State Machine Status bit must first
be checked to determine byte write or block erase com-
pletion, before the Byte Write or Erase Status bit are
checked for success.
If the Byte Write AND Erase Status bits are set to ‘‘1’’s
during a block erase attempt, an improper command se-
quence was entered. Attempt the operation again.
If V
PP
low status is detected, the Status Register must be
cleared before another byte write or block erase opera-
tion is attempted.
The V
PP
Status bit, unlike an A/D converter, does not
provide continuous indication of V
PP
level. The WSM in-
terrogates the V
PP
level only after the byte write or block
erase command sequences have been entered and in-
forms the system if V
PP
has not been switched on. The
V
PP
Status bit is not guaranteed to report accurate feed-
back between V
PPL
and V
PPH
.
12
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