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| 型號(hào)： | TAS5705PAPG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類(lèi)： | 音頻／視頻放大 |
| 英文描述： | 20 W, 2 CHANNEL, AUDIO AMPLIFIER, PQFP64 |
| 封裝： | 10 X 10 MM, GREEN, PLASTIC, HTQFP-64 |
| 文件頁(yè)數(shù)： | 56/72頁(yè) |
| 文件大小： | 1168K |
| 代理商： | TAS5705PAPG4 |
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SLOS549A – JUNE 2008 – REVISED SEPTEMBER 2009 ................................................................................................................................................ www.ti.com
TERMINAL FUNCTIONS (continued)
TERMINAL
TYPE
5-V
TERMINATION
DESCRIPTION
(1)
TOLERANT
(2)
NAME
NO.
DVDD
15, 33
P
3.3-V digital power supply
DVSS
20
P
Digital ground
DVSSO
26
P
Oscillator ground
FAULT
9
DO
Pullup
Overtemperature, overcurrent, and undervoltage fault reporting.
Active-low indicates fault. If high, normal operation.
GND
41, 42
P
Analog ground for power stage
GVDD_AB
5
P
Gate drive internal regulated output for AB channels
GVDD_CD
44
P
Gate drive internal regulated output for CD channels
HPL_PWM
37
DO
Headphone left-channel PWM output.
HPR_PWM
38
DO
Headphone right-channel PWM output.
HPSEL
30
DI
5-V
Headphone select, active-high. When a logic high is applied, device
enters headphone mode and speakers are MUTED (HARD MUTE).
When a logic LOW is applied, device is in speaker mode and
headphone outputs become line outputs or are disabled. When in line
out mode, this terminal functionality is disabled (see system control
register 2.
LRCLK
22
DI
5-V
Input serial audio data left/right clock (sampling rate clock)
MCLK
34
DI
5-V
MCLK is the clock master input. The input frequency of this clock can
range from 4.9 MHz to 49.2 MHz.
MUTE
21
DI
5-V
Pullup
Performs a soft mute of outputs, active-low. A logic low on this pin
sets the outputs equal to 50% duty cycle. A logic high on this pin
allows normal operation. The mute control provides a noiseless
volume ramp to silence. Releasing mute provides a noiseless ramp to
previous volume.
OC_ADJ
8
AO
Analog overcurrent programming. Requires 22-k
resistor to ground.
OSC_RES
19
AO
Oscillator trim resistor. Connect an 18.2-k
, 1% tolerance resistor to
DVSSO.
OUT_A
1, 64
O
Output, half-bridge A
OUT_B
60, 61
O
Output, half-bridge B
OUT_C
52, 53
O
Output, half-bridge C
OUT_D
48, 49
O
Output, half-bridge D
PDN
17
DI
5-V
Pullup
Power down, active-low. PDN powers down all logic, stops all clocks,
and stops output switching whenever a logic low is applied. When
PDN is released, the device powers up all logic, starts all clocks, and
performs a soft start that returns to the previous configuration
determined by register settings.
PGND_AB
62, 63
P
Power ground for half-bridges A and B
PGND_CD
50, 51
P
Power ground for half-bridges C and D
PLL_FLTM
12
AO
PLL negative loop filter terminal
PLL_FLTP
13
AI
PLL positive loop filter terminal
PVDD_A
2, 3
P
Power supply input for half-bridge output A (8 V–23 V)
PVDD_B
58, 59
P
Power supply input for half-bridge output B (8 V–23 V)
PVDD_C
54, 55
P
Power supply input for half-bridge output C (8 V–23 V)
PVDD_D
46, 47
P
Power supply input for half-bridge output D (8 V–23 V)
RESET
16
DI
5-V
Pullup
Reset, active-low. A system reset is generated by applying a logic
low to this terminal. RESET is an asynchronous control signal that
restores the DAP to its default conditions, sets the VALID outputs
low, and places the PWM in the hard-mute state (stops switching).
Master volume is immediately set to full attenuation. Upon the release
of RESET, if PDN is high, the system performs a 4–5-ms device
initialization and sets the volume at mute.
SCL
29
DI
5-V
I2C serial control clock input
6
Copyright 2008–2009, Texas Instruments Incorporated
Product Folder Link(s): TAS5705
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