參數(shù)資料
型號(hào): TAS5705PAPG4
廠商: TEXAS INSTRUMENTS INC
元件分類(lèi): 音頻/視頻放大
英文描述: 20 W, 2 CHANNEL, AUDIO AMPLIFIER, PQFP64
封裝: 10 X 10 MM, GREEN, PLASTIC, HTQFP-64
文件頁(yè)數(shù): 27/72頁(yè)
文件大?。?/td> 1168K
代理商: TAS5705PAPG4
A6
A5
A4
A3
A2
A1
A0
R/W ACK A7
A6
A5
A4
A3
A2
A1
A0
ACK
D7
D6
D5
D4
D3
D2
D1
D0 ACK
Start
Condition
Stop
Condition
Acknowledge
I CDevice Addressand
2
Read/WriteBit
Subaddress
DataByte
T0036-01
D7
D0 ACK
Stop
Condition
Acknowledge
I CDevice Addressand
2
Read/WriteBit
Subaddress
LastDataByte
A6
A5
A1
A0 R/W ACK A7
A5
A1
A0
ACK D7
ACK
Start
Condition
Acknowledge
FirstDataByte
A4
A3
A6
OtherDataBytes
ACK
Acknowledge
D0
D7
D0
T0036-02
www.ti.com ................................................................................................................................................ SLOS549A – JUNE 2008 – REVISED SEPTEMBER 2009
Supplying a subaddress for each subaddress transaction is referred to as random I2C addressing. The TAS5705
also supports sequential I2C addressing. For write transactions, if a subaddress is issued followed by data for
that subaddress and the 15 subaddresses that follow, a sequential I2C write transaction has taken place, and the
data for all 16 subaddresses is successfully received by the TAS5705. For sequential I2C write transactions, the
subaddress then serves as the start address, and the amount of data subsequently transmitted, before a stop or
start is transmitted, determines how many subaddresses are written. As was true for random addressing,
sequential addressing requires that a complete set of data be transmitted. If only a partial set of data is written to
the last subaddress, the data for the last subaddress is discarded. However, all other data written is accepted;
Single-Byte Write
As shown in Figure 38, a single-byte data write transfer begins with the master device transmitting a start
condition followed by the I2C device address and the read/write bit. The read/write bit determines the direction of
the data transfer. For a write data transfer, the read/write bit is a 0. After receiving the correct I2C device address
and the read/write bit, the DAP responds with an acknowledge bit. Next, the master transmits the address byte or
bytes corresponding to the TAS5705 internal memory address being accessed. After receiving the address byte,
the TAS5705 again responds with an acknowledge bit. Next, the master device transmits to the memory address
being accessed the data byte to be written. After receiving the data byte, the TAS5705 again responds with an
acknowledge bit. Finally, the master device transmits a stop condition to complete the single-byte data write
transfer.
Figure 38. Single-Byte Write Transfer
Multiple-Byte Write
A multiple-byte data write transfer is identical to a single-byte data write transfer except that multiple data bytes
are transmitted by the master device to the DAP as shown in Figure 39. After receiving each data byte, the
TAS5705 responds with an acknowledge bit.
Figure 39. Multiple-Byte Write Transfer
Copyright 2008–2009, Texas Instruments Incorporated
33
Product Folder Link(s): TAS5705
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