參數(shù)資料
型號: TAS5705PAPG4
廠商: TEXAS INSTRUMENTS INC
元件分類: 音頻/視頻放大
英文描述: 20 W, 2 CHANNEL, AUDIO AMPLIFIER, PQFP64
封裝: 10 X 10 MM, GREEN, PLASTIC, HTQFP-64
文件頁數(shù): 38/72頁
文件大?。?/td> 1168K
代理商: TAS5705PAPG4
www.ti.com ................................................................................................................................................ SLOS549A – JUNE 2008 – REVISED SEPTEMBER 2009
By default, bits 2:0 have the value 000; that means the bank switch is disabled. In that state, any update to
locations 0x29–0x3F go into the DAP. A write to register 0x50 with bits 2:0 being 001, 010, or 011 brings the
system into the coefficient-bank-update state update bank1, update bank2, or update bank3, respectively. Any
subsequent write to locations 0x29–0x3F updates the coefficient banks stored outside the DAP. After updating all
the three banks, the system controller should issue a write to register 0x50 with bits 2:0 being 100; this changes
the system state to automatic bank update. In automatic bank update, the TAS5705 automatically swaps banks
based on the sample rate.
In the headphone mode, speaker equalization and DRC are disabled, and they are restored on returning to the
speaker mode.
Command sequences for initialization can be summarized as follows:
1.
Enable factory trim for internal oscillator: Write to register 0x1B with a value 0x00.
2.
Update coefficients: Coefficients can be loaded into DAP RAM using the manual bank mode.
OR
Use automatic bank mode.
(a)
Enable bank-1 mode: Write to register 0x50 with 0x01. Load the 32-kHz coefficients. TI ALE
can generate coefficients.
(b)
Enable bank-2 mode: Write to register 0x50 with 0x02. Load the 48-kHz coefficients.
(c)
Enable bank-3 mode: Write to register 0x50 with 0x03. Load the other coefficients.
(d)
Enable automatic bank switching by writing to register 0x50 with 0x04.
3.
Bring the system out of all-channel shutdown: Write 0 to bit 6 of register 0x05.
4.
Issue master volume: Write to register 0x07 with the volume value (0 db = 0x30).
Interchannel Delay (ICD) Settings
Table 6. Recommended ICD Settings
Mode
Description
ICD1
ICD2
ICD3
ICD4
ICD5
ICD6
BD
2 BTL channels, internal
A(L+) = –18
C(R+) = 24 =
B(L–) = –24 =
D(R–) = 18 =
SM(S–) = –3 = SP(S+) = 3 =
power stage only, BD
(0xB8)
(0x60)
(0xA0)
(0x48)
(0xF4)
(0x0C)
mode
AD
2 internal BTL channels,
A(L+) = –21 =
C(R+) = 21
B(L–) = –21 =
D(R–) = 21 =
SM(S–) = 0 =
SP(S+) = 0 =
1 external BTL channel
(0xAC)
(0x54)
(0xAC)
(0x54)
(0x00)
using PBTL TAS5102,
AD mode
Copyright 2008–2009, Texas Instruments Incorporated
43
Product Folder Link(s): TAS5705
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