參數(shù)資料
型號(hào): TAS5110ADADR
廠商: Texas Instruments, Inc.
英文描述: PurePath Digital AMPLIFIER TAS5110A 50-W DIGITAL AMPLIFIER POWER STAGE
中文描述: PurePath Digital數(shù)字功放TAS5110A 50 - W數(shù)字放大器功率級(jí)
文件頁數(shù): 5/17頁
文件大?。?/td> 165K
代理商: TAS5110ADADR
TAS5110A
SLES079A
APRIL 2003
REVISED MAY 2003
www.ti.com
5
Terminal Functions
TERMINAL
NAME
DAD
NO.
6
5
19
30
11
8, 9,
10
I/O
DESCRIPTION
BIAS_A
BIAS_B
BOOTSTRAPA
BOOTSTRAPB
DVDD
DVSS
I
I
Connect external resistor to DVSS.
Connect external resistor to DVSS.
Bootstrap capacitor pin for H-bridge A
Bootstrap capacitor pin for H-bridge B
3.3-V digital voltage supply for logic
Digital ground for logic is internally connected to PVSS. All three pins must be tied together but not
connected externally to PVSS. See Figure 5.
O
O
ERR1
ERR0
LDROUTA
LDROUTB
OUTPUTA
OUTPUTB
PVDDA1
PVDDA2
PVDDB1
PVDDB2
PVSS
PWDN
PWM_AM
PWM_AP
PWM_BP
PWM_BM
RESET
14
13
18
31
O
O
O
O
O
O
I
I
I
I
I
I
Error/warning report indicator. This output is open drain with internal pullup resistor.
Error/warning report indicator. This output is open drain with internal pullup resistor.
Low-voltage drop-out regulator output A (not to be used to supply current to external circuitry)
Low-voltage drop-out regulator output B (not to be used to supply current to external circuitry)
H-bridge output A
H-bridge output B
High-voltage power supply, H-bridge A
High-voltage power supply for low-dropout voltage regulator A-side
High-voltage power supply, H-bridge B
High-voltage power supply for low-dropout voltage regulator B-side
High-voltage power supply ground
Power down = 0, normal mode = 1
PWM input A(
)
PWM input A(+)
PWM input B(+)
PWM input B(
)
Reset and mute mode = 0, normal mode = 1; when in reset mode, H-bridge MOSFETs are in low-low
output state. Asserting the RESET signal low causes all fault conditions to be cleared.
22, 23
26, 27
20, 21
17
28, 29
32
24, 25
4
15
16
1
2
3
SHUTDOWN
12
O
Device is in shutdown due to fault condition, normal mode = 1, shutdown = 0; when device is in
shutdown mode the H-bridge MOSFETs are in low-low output state. The latched output can be
cleared by asserting the RESET signal. This output is open drain with internal pullup resistor.
A filter capacitor must be added between the VRFILT and DVSS pins.
NOTE:The four PWM inputs: PWM_AP, PWM_AM, PWM_BP, and PWM_BM must always be connected to the TAS50xx output pins and never
left floating. Floating PWM input pins cause an illegal PWM input state signal to be asserted.
Dual pins: OUTPUTA, OUTPUTB, PVDDA1, and PVDDB1 must have both pins connected externally to the same point on the circuit board,
respectively. Both PVSS pins must also be connected ogether externally. These multiple pins are for the high-current DMOS output devices.
Failure to connect all the multiple pins to the same respective node results in excessive current flow in the internal bond wires and can cause
the device to fail. All electrical characteristics are specified and measured with all of the multiple pins of each type connected to a single node.
VRFILT
7
O
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