參數(shù)資料
型號(hào): TAS5110ADADR
廠商: Texas Instruments, Inc.
英文描述: PurePath Digital AMPLIFIER TAS5110A 50-W DIGITAL AMPLIFIER POWER STAGE
中文描述: PurePath Digital數(shù)字功放TAS5110A 50 - W數(shù)字放大器功率級(jí)
文件頁數(shù): 10/17頁
文件大?。?/td> 165K
代理商: TAS5110ADADR
TAS5110A
SLES079A
APRIL 2003
REVISED MAY 2003
www.ti.com
10
RECOMMENDED OPERATING CONDITIONS
(maximum output power = 50 W (RMS), TJ = 25
°
C)
Thermal Data
(1)
MIN
NOM
MAX
UNIT
TJ(SD)
Shutdown junction temperature
150
°
C
TJ(W)
Warning unction temperature
125
°
C
TC
R
θ
JC(2)
R
θ
JA(2)
(1)One of the most influential components on the thermal performance of a package is board design. In order to take full advantage of the heat
dissipating abilities of the PowerPAD packages, a board must be used that acts similar to a heat sink and allows for the use of the exposed (and
solderable), deep downset pad. See Appendix A of the
PowerPAD Thermally Enhanced Package
technical brief, TI literature number SLMA002.
(2)For the DAD package.
Operating emperature
Commercial
0
25
70
°
C
Thermal resistance junction-to-case
2 oz trace and copper pad without solder
2 oz. trace and copper pad without solder
1.6
°
C/W
Thermal resistance unction-to-ambient
44.3
°
C/W
R
L
= 6
to 8
MIN
NOM
MAX
UNIT
Digital
DVDD to DVSS
3
3.3
3.6
V
PVDDA2 to PVSS
16.5
22
26.5
Supply voltage
Regulator
PVDDB2 to PVSS
16.5
22
26.5
V
PVDDA2 to PVSS(1)
10.5
16.5
PVDDB2 to PVSS(1)
10.5
16.5
(1)Connect LDROUTA to PVDDA2 and connect LDROUTB to PVDDB2. Under this condition, the H-bridge forward on-state resistance s ncreased.
This increases internal power dissipation. Maximum output power may need to be reduced to meet thermal conditions.
Maximum Available Power at Common Load Impedances for the DAD Package Unclipped (0 dB) Level
(1)
LOADIMPEDANCE
LOAD IMPEDANCE
(
)
6
PVDAA1/PVDDB1
(VDC)
27
APPROXIMATEMAXIMUM
APPROXIMATE MAXIMUM
OUTPUT POWER (W)
50
THD+N AT MAXIMUM POWER
AND 1-kHz INPUT(2)
< 10%
6
27
43
< 0.09%
8
27
34
< 0.09%
(1)Dependent on board design and component selection
(2)Test conditions are described in the
Thermal Methodology for the 32-Pin DAD Package 50 W, 6-
Test
.
STATIC DIGITAL SPECIFICATIONS
RESET, PWDN, PWM_AP, PWM_AM, PWM_BP, PWM_BM, T
J
= 25
°
C, DVDD = 3.3 V
PARAMETERS
MIN
MAX
UNIT
VIH
High-level input voltage
2
V
VIL
Low-level input voltage
0.8
V
Input leakage current
10
10
μ
A
ERR0, ERR1, SHUTDOWN, (Open Drain With Internal Pullup Resistor) T
J
= 25
°
C, DVDD = 3.3 V)
PARAMETERS
MIN
MAX
UNIT
Internal pullup resistors from SHUTDOWN, ERR0, ERR1 to DVDD
15
k
VOL
Low-level output voltage (IO = 4 mA)
0.4
V
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