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參數(shù)資料
| 型號： | T8534 |
| 廠商： | Lineage Power |
| 英文描述： | Quad Programmable Line Card Signal Processor(四通道可編程線卡信號處理器) |
| 中文描述： | 四線卡可編程信號處理器（四通道可編程線卡信號處理器） |
| 文件頁數(shù)： | 41/48頁 |
| 文件大?。?/td> | 1809K |
| 代理商： | T8534 |
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Preliminary Data Sheet
July 2000
Signal Processor
T8533/34 Quad Programmable Line Card
Lucent Technologies Inc.
41
Software Interface
(continued)
Table 18. Control Bit Definitions
(continued)
Control Name
(Address)
NESCTRL
(word 137)
Bit
Assignments
Function
3—7
2
0—1
Load as 0s.
Enable near-end speech detector. Defaults to 1 (active).
Threshold for the near-end speech detector.
Default is 2 (
6 dB).
Bit
Number
1
0
0
1
1
Bit
Number
7
0
0
1
1
Function (dB)
(Threshold =)
0
0
1
0
1
0.0
3.5
6.0
9.5
LMSGAIN
(word 138)
6—7
Length of echo canceller (8, 16, 32, 64 taps).
Defaults to 3 (64 taps).
Function
6
0
1
0
1
8 taps
16 taps
32 taps
64 taps
3—5
Relative adaptive gain of the two IIR taps in the echo canceller. Defaults to 5. A
setting of 0 provides no adaptive loop gain.
Loop gain for adaptation algorithm. Default is 6.
0—2
Bit Number
2
1
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
Function
(Gain =)
0.0078
0.0156
0.0313
0.0625
0.1250
0.2500
0.5000
1.000
0
0
1
0
1
0
1
0
1
TDETCTRL
(word 139)
6—7
5
Load as 0.
This bit being set allows the echo canceller coefficients developed off-line during
a data call to be captured and saved for potential use during the next data call.
Default is 0 (do not capture).
This bit enables the echo canceller to continue to adapt during a data call.
Default is 0 (do not adapt during a data call).
This bit, when set, enables the use of the internal logic to determine the proper
time for the off-line adaptation during a data call. Default is 0.
Selects the internal set of hybrid balance network coefficients to use on a data
call. Default is 0.
This bit, when set to a 1, clears the H register at the start of a data call. Default is
0.
This bit being set freezes the echo canceller. Default is 0.
4
3
2
1
0
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