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參數(shù)資料
| 型號： | T8534 |
| 廠商： | Lineage Power |
| 英文描述： | Quad Programmable Line Card Signal Processor(四通道可編程線卡信號處理器) |
| 中文描述： | 四線卡可編程信號處理器（四通道可編程線卡信號處理器） |
| 文件頁數(shù)： | 39/48頁 |
| 文件大?。?/td> | 1809K |
| 代理商： | T8534 |
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Preliminary Data Sheet
July 2000
Signal Processor
T8533/34 Quad Programmable Line Card
Lucent Technologies Inc.
39
Software Interface
(continued)
Table 17. Memory Mapping
(continued)
Table 18. Control Bit Definition
The following table shows the control bit assignments in the memory control addresses. In all control bit cases, the
bit being set places the function into the active mode as defined in the function column.
Control Name
Address
(decimal)
Number
of Bits
Used
6
Default
Value
Name/Description
SLICWR
159
0x00
Data to be written to the SLIC latches if the corresponding
bit is set in the SLICTS control word.
Current actual state of the SLIC pins. This will be the same
as SLICWR for those pins configured as outputs. All other
positions will reflect the actual state of the external pin. A
write operation to this word will be ignored, and within one
PCM frame (125
μ
s), the data will be overwritten.
Test address for serial interface verification.
Read-only indicator of a data call in progress. Do not write
this register.
Factory test only, do not access.
SLICRD
160
6
—
VERIFY
DATACALL
162
167
8
1
—
—
—
254—255
16
—
Control Name
(Address)
HBALTAPS
(words 0—127)
RESCTRL
(word 128)
Bit
Assignment(s)
0—1023
Function
Balance impedance coefficients. Default value is 0x00 for all bytes except for
addresses 3 and 5, which are 0x80, and address 69, which is 0x88.
Not used, load as 0s.
A one resets the state associated with special data call processing.
A one resets the echo canceller coefficients to 0 when channel is active.
A one resets all other internal states.
Reset all control addresses to default values. Note that setting this bit will result
in it and all others of this word becoming cleared on the next PCM frame as a
normal part of this control reset functionality. Also, the state reset bits (1—3) are
cleared before they are acted upon if this bit is raised; hence, it is not possible to
reset both state and control by writing 0x0F to RESCTRL. If such an action is
desired, it is necessary to first reset control by writing 0x01 and then, in a sub-
sequent frame, write first 0x0E and then 0x00. Alternatively, hardware reset can
be used to reset all control and state.
4—7
3
2
1
0
It is necessary to wait at least 256
μ
s after asserting this bit before initiating any
other serial I/O transactions.
Load as 0s.
Active/Standby mode. A 0 causes the channel to enter standby (low power)
mode and disables the PCM interface for this channel. A 1 activates the channel
and the corresponding PCM bus interface. Default is 0.
CHACTIVE
(word 129)
1—7
0
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