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參數(shù)資料
| 型號： | T8531A |
| 元件分類： | Codec |
| 英文描述： | T8531A/8532 Multichannel Programmable Codec Chip Set |
| 中文描述： | T8531A/8532多通道可編程解碼器芯片組 |
| 文件頁數(shù)： | 40/50頁 |
| 文件大?。?/td> | 888K |
| 代理商： | T8531A |
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40
Agere Systems Inc.
Preliminary Data Sheet
September 2001
Codec Chip Set
T8531A/T8532 Multichannel Programmable
Software Interface
(continued)
Table 33. Bits 15:8 of T8531A Board Control Word 1 at 0x1FFE
Table 34. Bits 7:0 of T8531A Board Control Word 1 at 0x1FFE
Notes:
All bits in board control register 1 will be zeros upon hardware reset.
In OSD loopback mode, OSDR0, OSDR1, OSDR2, and OSDR3 are looped back with a delay of two OSCLK clock cycles to OSDX0, OSDX1,
OSDX2, and OSDX3, respectively.
Test modes are for production testing only.
μ
-law/A-law companding mode provides 8 bits of PCM data with the first bit (bit 1) defined as the MSB and the last bit (bit 8) as the LSB. Bit 1 is
the sign bit, bits 2 through 4 are the chord bits, and bits 5 through 8 are the interval bits. In linear mode, the
μ
-law/A-law conversion in the PCM
interface block is disabled and 16 bits of linear PCM data are provided. In linear mode, bit 1 is the MSB and the sign bit, bits 2 through 14 are
the intervals, and bits 15 and 16 are insignificant. Each interval represents 0.0001362745 Vrms with 8031 intervals being the maximum signal
output of 3 dBm0. Negative values are two’s complement of positive values.
X = don’t care.
Bit Number
12
—
—
—
—
—
—
—
—
—
—
Function
15
0
1
—
—
—
—
—
—
—
—
14
—
—
—
—
—
—
—
—
—
—
13
—
—
—
—
—
—
—
—
—
—
11
—
—
0
1
—
—
—
—
—
—
10
—
—
—
—
0
1
—
—
—
—
9
—
—
—
—
—
—
0
1
—
—
8
—
—
—
—
—
—
—
—
0
1
Normal operation
Soft reset
Normal operation
TZ test mode
Normal operation
RX dither circuit off
Normal operation
Nodecim test mode
Normal operation
Linear mode
Bit Number
4
—
—
x
0
1
—
—
—
—
—
Function
7
0
1
—
—
—
—
—
—
—
—
6
X
X
X
X
X
X
X
X
X
X
5
—
—
0
1
1
—
—
—
—
—
3
—
—
—
—
—
C1
—
—
—
—
2
—
—
—
—
—
C0
—
—
—
—
1
—
—
—
—
—
—
0
1
—
—
0
—
—
—
—
—
—
—
—
0
1
Delayed data timing
Nondelayed data timing
μ
-law
A-law, including even bit inversion
A-law, no even bit inversion
C1C0 = card address in binary
Reserved
Normal operation
Normal operation
Loopback at OSD
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| T8531 | T8502 and T8503 Dual PCM Codecs with Filters |
| T8532 | T8502 and T8503 Dual PCM Codecs with Filters |
| T8533 | T8533/34 Quad Programmable Line Card Signal Processor |
| T8534 | T8533/34 Quad Programmable Line Card Signal Processor |
| T8535B | T8535B/T8536B Quad Programmable Codec |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| T8532 | 制造商:AGERE 制造商全稱:AGERE 功能描述:T8531A/8532 Multichannel Programmable Codec Chip Set |
| T8533 | 制造商:AGERE 制造商全稱:AGERE 功能描述:T8533/34 Quad Programmable Line Card Signal Processor |
| T85331G | 制造商:BITECH 制造商全稱:Bi technologies 功能描述:Thick Film Super Low Profile SIP Resistor Networks |
| T85331J | 制造商:BITECH 制造商全稱:Bi technologies 功能描述:Thick Film Super Low Profile SIP Resistor Networks |
| T8534 | 制造商:AGERE 制造商全稱:AGERE 功能描述:T8533/34 Quad Programmable Line Card Signal Processor |
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