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參數(shù)資料
| 型號： | T7295-1 |
| 廠商： | Lineage Power |
| 英文描述： | E3 Integrated Line Receiver(E3 集成線接收器) |
| 中文描述： | 綜合線接收E3展（E3展集成線接收器） |
| 文件頁數(shù)： | 9/14頁 |
| 文件大?。?/td> | 321K |
| 代理商： | T7295-1 |
Data Sheet
February 1997
T7295-1 E3 Integrated Line Receiver
9
Lucent Technologies Inc.
Timing Recovery
(continued)
Loss-of-Signal Detection
(continued)
Phase Hits
In response to a 180 degree phase hit in the input data,
the T7295-1 returns to error-free operation in less than
2 ms. During the reacquisition time, RLOS may tempo-
rarily be indicated.
Interference Immunity
The T7295-1 complies with the interference test
detailed in G.703 and detailed in Figure 7. The two
data generators are asynchronous.
5-2640(C).ar.2
Figure 7. Test Setup for Interference Immunity
In-Circuit Test Capability
When pulled low, the
ICT
pin forces all digital outputs
(RCLK, RPDATA, RNDATA, RLOS, RLOL pins) into a
high output impedance state. This feature allows in-
circuit testing to be done on neighboring devices with-
out concern for T7295-1 device output damage. When
forced high, the
ICT
pin does not affect device opera-
tion. An internal pull-up device (nominally 50 k
) is pro-
vided on this pin; therefore, users can leave this pin
unconnected for normal operation. This is the only pin
for which internal pull-up/pull-down is provided.
Board Layout Considerations
Power Supply Bypassing
Figure 8 illustrates the recommended power supply
bypassing network. A 0.1
μ
F (C2) capacitor bypasses
the digital supplies. The analog supply V
DDA
is
bypassed by using a 0.1
μ
F (C1) capacitor and a shield
bead that removes significant amounts of high-
frequency noise generated by the system and by the
device logic. Good-quality, high-frequency (low lead
inductance) capacitors should be used. Finally, it is
most important that all ground connections be made to
a low-impedance ground plane.
5-2637(C).ar.1
* Recommended shield beads are the FairRite
2643000101 or the
FairRite 2743019446 (surface mount) or equivalent.
FairRite
is a registered trademark of FairRite Products Corporation.
Figure 8. Recommended Power Supply
Bypassing Network
Receive Input
The connections to the receive input pin must be care-
fully considered. Noise coupling must be minimized
along the path from the signal entering the board to the
input pin. Any noise coupled into the T7295-1 input
directly degrades the signal-to-noise ratio of the input
signal and may degrade sensitivity.
PLL Filter Capacitor
The PLL filter capacitor between pins LPF1 and LPF2
must be placed as close to the chip as possible (within
1.2 cm is recommended). The LPF1 and LPF2 pins are
adjacent, allowing for short-lead lengths with no cross-
overs to the external capacitor. Noise coupling into the
LPF1 and LPF2 pins may degrade PLL performance.
CABLE
LOSS
+
0 dB TO 12.0 dB
AT 17,184 kHz
LUCENT
T7295-1
ERROR
DETECTOR
20 dB
ATTENUATION
PRBS
2
23
– 1
PRBS
2
23
– 1
GND
A
GND
D
GND
C
V
DDA
V
DDC
V
DDD
T7295-1
C1
0.1 μF
SHIELD BEAD*
C2
0.1 μF
+5 V
SENSITIVE NODE
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