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參數(shù)資料
| 型號： | T7295-1 |
| 廠商： | Lineage Power |
| 英文描述： | E3 Integrated Line Receiver(E3 集成線接收器) |
| 中文描述： | 綜合線接收E3展（E3展集成線接收器） |
| 文件頁數(shù)： | 8/14頁 |
| 文件大?。?/td> | 321K |
| 代理商： | T7295-1 |
Data Sheet
February 1997
T7295-1 E3 Integrated Line Receiver
8
Lucent Technologies Inc.
Timing Recovery
(continued)
Acquisition Time
If a valid input signal is already present at the RIN input,
the maximum time between the application of device
power at 4.5 V and error-free operation is 20 ms. If
power has already been applied, the interval between
the application of valid data and error-free operation is
4 ms.
False Lock Immunity
False lock is defined as the condition where a PLL
recovered clock obtains stable phase-lock at a frequency
not equal to the incoming data rate. The T7295-1 device
uses a combination frequency/phase-lock architecture to
prevent false lock. The PLL acquisition aid circuitry mon-
itors the PLL clock frequency relative to the EXCLK ref-
erence frequency. If the frequency difference between
the EXCLK and PLL clock exceeds approximately
±
0.5%, correction circuitry forces reacquisition of the
proper frequency and phase.
Loss-of-Lock Indication
The RLOL alarm is activated if the difference between
the PLL clock and the EXCLK frequency exceeds
approximately
±
0.5%. A high RLOL output indicates that
the PLL acquisition circuit is working to bring the PLL
into proper frequency lock. RLOL remains high until fre-
quency lock has occurred; however, the minimum RLOL
pulse width is 32 clock cycles.
Loss-of-Signal Detection
Figure 1 shows that analog and digital methods of loss-
of-signal (LOS) detection are combined to create the
RLOS alarm output. RLOS is set if either the analog or
digital detection circuitry indicates LOS has occurred.
Analog LOS Detection
The analog LOS detector monitors the peak input signal
amplitude. RLOS makes a high-to-low transition (input
signal regained) when the input signal amplitude
exceeds the loss-of-signal threshold defined in Table 5.
The RLOS low-to-high transition (input signal lost)
occurs at a level typically 1.0 dB below the high-to-low
transition level. This hysteresis prevents RLOS chatter-
ing. Once set, the RLOS alarm remains high for at least
32 clock cycles, allowing for system detection of a loss-
of-signal condition without the use of an external latch.
To allow for varying levels of noise and crosstalk in dif-
ferent applications, three loss-of-signal threshold set-
tings are available using the LOSTHR pin. Setting
LOSTHR = V
DD
provides the lowest loss-of-signal
threshold; LOSTHR = V
DD
/2 (can be produced using
two 50 k
±
10% resistors as a voltage divider between
V
DDD
and GND
D
) provides an intermediate threshold;
and LOSTHR = GND provides the highest threshold.
The LOSTHR pin must be set to its desired value at
powerup and must not be changed during operation.
Table 5. Analog Loss-of-Signal Thresholds
Notes:
The RLOS alarm is an indication of the presence of an input signal,
not a bit error rate indication. Table 2 gives the minimum input ampli-
tude needed for error-free operation (BER < 1e
–
9
). Independent of
the RLOS state, the device will attempt to recover correct timing and
data.
The RLOS low-to-high transition typically occurs 1 dB below the high-
to-low transition.
Digital LOS Detection
In addition to the signal amplitude monitoring of the
analog LOS detector, the digital LOS detector monitors
the recovered data 1s density. The RLOS alarm goes
high if 160
±
32 or more consecutive 0s occur in the
receive data stream. The alarm goes low when at least
eight 1s occur in a string of 32 consecutive bits. This
hysteresis minimizes RLOS chattering and guarantees
a minimum RLOS pulse width of 32 clock cycles.
Note, however, that RLOS chatter can still occur. When
REQB = 1, input signal levels above the analog RLOS
threshold can still be low enough to result in a high bit
error rate. The resultant data stream (containing errors)
can temporarily activate the digital LOS detector, and
RLOS chatter can occur. Therefore, RLOS should not
be used as a bit error rate monitor. RLOS chatter can
also occur when RLOL is activated (high).
The T7295-1EL and T7295-1PL devices do not meet
the digital LOS detection requirements for HDB3
encoding. This is corrected in the version of silicon that
is code marked T7295-1EL2 and T7295-1PL2.
Data
Rate
REQB LOSTHR
Threshold
Min
60
40
25
45
30
20
Unit
Max
220
145
90
175
115
70
E3
34.368
Mbits/s
0
0
mV pk
mV pk
mV pk
mV pk
mV pk
mV pk
V
DD
/2
V
DD
0
V
DD
/2
V
DD
1
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