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參數資料
| 型號： | T4312816B |
| 廠商： | TM Technology, Inc. |
| 英文描述： | 8M x 16 SDRAM 2M x 16bit x 4Banks Synchronous DRAM |
| 中文描述： | 8米× 16 SDRAM的2米x 16Bit的X 4Banks同步DRAM |
| 文件頁數： | 8/70頁 |
| 文件大?。?/td> | 688K |
| 代理商： | T4312816B |
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TE
CH
tm
6 Write command
(RAS# = "H", CAS# = "L", WE# = "L", BAs = Bank, A10 = "L", A0-A8 = Column Address)
The Write command is used to write a burst of data on consecutive clock cycles from an active row in an
active bank. The bank must be active for at least t
RCD
(min.) before the Write command is issued. During write
bursts, the first valid data-in element will be registered coincident with the Write command. Subsequent data
elements will be registered on each successive positive clock edge (refer to the following figure). The DQs
remain with high-impedance at the end of the burst unless another command is initiated. The burst length and
burst sequence are determined by the mode register, which is already programmed. A full-page burst will
continue until terminated (at the end of the page it will wrap to column 0 and continue).
T4312816B
TM Technology Inc. reserves the right
P. 8
to change products or specifications without notice.
Publication Date: FEB. 2007
Revision: A
CLK
COMMAND
T0
T 1
T2
T3
T4
T5
T6
T7
T8
DIN A3
NOP
WRITE A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
DIN A0
DIN A1
DIN A2
DQ0 - DQ3
The first data element and the write
are registered on the same clock edge.
Burst Write Operation
(Burst Length = 4, CAS# Latency = 1, 2, 3)
Extra data is masked.
don't care
BankPrecharge/PrechargeAll, or Read command before the end of the burst length. An interrupt coming from
Write command can occur on any clock cycle following the previous Write command (refer to the following
figure).
A write burst without the auto precharge function may be interrupted by a subsequent Write,
CLK
COMMAND
T0
T 1
T2
T3
T4
T5
T6
T7
T8
DIN B2
NOP
WRITE A
NOP
NOP
NOP
NOP
NOP
WRITE B
NOP
DIN A0
DIN B0
DIN B1
DQ's
DIN B3
1 Clk Interval
Write Interrupted by a Write
(Burst Length = 4, CAS# Latency = 1, 2, 3)
cycle after the clock edge in which the last data-in element is registered. In order to avoid data contention, input
data must be removed from the DQs at least one clock cycle before the first read data appears on the outputs
(refer to the following figure). Once the Read command is registered, the data inputs will be ignored and writes
will not be executed.
The Read command that interrupts a write burst without auto precharge function should be issued one
CLK
COMMAND
T0
T 1
T2
T3
T4
T5
T6
T7
T8
NOP
WRITE A
NOP
NOP
NOP
NOP
NOP
READ B
NOP
DIN A0
don't care
DOUT B2
DOUT B0
DOUT B1
DOUT B3
DIN A0
don't care
don't care
DOUT B2
DOUT B0
DOUT B1
DOUT B3
Input data for the write is masked.
Input data must be removed from the DQ's at least one clock
cycle before the Read data appears on the outputs to avoid
data contention.
CAS# latency=2
tCK2, DQ's
CAS# latency=3
tCK3, DQ's
Write Interrupted by a Read
(Burst Length = 4, CAS# Latency = 2, 3)
相關PDF資料 |
PDF描述 |
|---|---|
| T4312816B-6S | 8M x 16 SDRAM 2M x 16bit x 4Banks Synchronous DRAM |
| T4312816B-6SG | 8M x 16 SDRAM 2M x 16bit x 4Banks Synchronous DRAM |
| T4312816B-7S | 8M x 16 SDRAM 2M x 16bit x 4Banks Synchronous DRAM |
| T4312816B-7SG | 8M x 16 SDRAM 2M x 16bit x 4Banks Synchronous DRAM |
| T431616A | 1M x 16 SDRAM |
相關代理商/技術參數 |
參數描述 |
|---|---|
| T4312816B-6S | 制造商:TMT 制造商全稱:TMT 功能描述:8M x 16 SDRAM 2M x 16bit x 4Banks Synchronous DRAM |
| T4312816B-6SG | 制造商:TMT 制造商全稱:TMT 功能描述:8M x 16 SDRAM 2M x 16bit x 4Banks Synchronous DRAM |
| T4312816B-7S | 制造商:TMT 制造商全稱:TMT 功能描述:8M x 16 SDRAM 2M x 16bit x 4Banks Synchronous DRAM |
| T4312816B-7SG | 制造商:TMT 制造商全稱:TMT 功能描述:8M x 16 SDRAM 2M x 16bit x 4Banks Synchronous DRAM |
| T4314 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TRIANGULAR TYPE |
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