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參數(shù)資料
| 型號(hào)： | SYM53C875E |
| 廠商： | LSI Corporation |
| 英文描述： | PCI-Ultra SCSI I/O Processor(PCI-Ultra SCSI I/O 處理器) |
| 中文描述： | 的PCI -超的SCSI I / O處理器（個(gè)PCI -超的SCSI的I / O處理器） |
| 文件頁(yè)數(shù)： | 62/243頁(yè) |
| 文件大?。?/td> | 1362K |
| 代理商： | SYM53C875E |
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PCI Functional Description
Configuration Registers
3-12
SYM53C875/875E Data Manual
Register 2Ch
Subsystem Vendor ID (SSVID)
Read Only
T his register supports subsystem identification,
which has a default value of 0000h in the
SYM53C875 and 1000h in the SYM53C875E
(see Mad Bus Programming in Chapter 4). To
write to this register, connect a 4.7 K
resistor
between the MAD(6) pin and V
ss
and leave the
MAD(4) pin unconnected. T he MAD(6) and
MAD(4) pins have internal pull-up resistors and
are sensed shortly after the deassertion of chip
reset. In revisions before Rev. G of the
SYM53C875, the MAD(6) and MAD(4) pins do
not support the SSID and SSVID configurations,
and only values of 0000h can be found in the Sub-
system Data register.
Register 2Eh
Subsystem ID (SSID)
Read Only
T his register supports subsystem identification,
which has a default value of 0000h in the
SYM53C875 and 1000h in the SYM53C875E
(see Mad Bus Programming in Chapter 4). To
write to this register, connect a 4.7 K
resistor
between the MAD(6) pin and V
ss
and leave the
MAD(4) pin unconnected. T he MAD(6) and
MAD(4) pins have internal pull-up resistors and
are sensed shortly after the deassertion of chip
reset. In revisions before Rev. G of the
SYM53C875, the MAD(6) and MAD(4) pins do
not support the SSID and SSVID configurations,
and only values of 0000h can be found in the Sub-
system Data register.
Register 30h
Expansion ROM Base Address
Read/Write
T his four-byte register handles the base address
and size information for expansion ROM. It func-
tions exactly like the Base Address Zero and Base
Address One registers, except that the encoding of
the bits is different. T he upper 21 bits correspond
to the upper 21 bits of the expansion ROM base
address.
T he Expansion ROM Enable bit, bit 0, is the only
bit defined in this register. T his bit is used to con-
trol whether or not the device accepts accesses to
its expansion ROM. When the bit is set, address
decoding is enabled, and a device can be used with
or without an expansion ROM depending on the
system configuration. To access the external mem-
ory interface, the Memory Space bit in the Com-
T he host system detects the size of the external
memory by first writing the Expansion ROM Base
Address register with all ones and then reading
back the register. T he SYM53C875 will respond
with zeros in all don’t care locations. T he ones in
the remaining bits represent the binary version of
the external memory size. For example, to indicate
an external memory size of 32 K B, this register,
when written with ones and read back, will return
ones in the upper 17 bits.
Register 34h
Capability Pointer
Read Only
T his register provides an offset into the function’s
PCI Configuration Space for the location of the
first item in the capabilities linked list. Only the
SYM53C875E sets this register to 40h. T he capa-
bility pointer replaces the General Purpose Pin
Control Register in earlier revisions of the
SYM53C875.
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