參數(shù)資料
型號(hào)： SYM53C875E
廠商： LSI Corporation
英文描述： PCI-Ultra SCSI I/O Processor(PCI-Ultra SCSI I/O 處理器)
中文描述： 的PCI -超的SCSI I / O處理器（個(gè)PCI -超的SCSI的I / O處理器）
文件頁(yè)數(shù)： 104/243頁(yè)
文件大小： 1362K
代理商： SYM53C875E
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SCSI Operating Registers
5-18
SYM53C875/875E Data Manual
Register 0C (8C)
DMA Status (DSTAT )
Read Only
Reading this register will clear any bits that are set
at the time the register is read, but will not neces-
sarily clear the register because additional inter-
rupts may be pending (the SYM53C875 stacks
interrupts). T he DIP bit in the IST AT register will
also be cleared. DMA interrupt conditions may be
individually masked through the DIEN register.
When performing consecutive 8-bit reads of the
DST AT , SIST 0 and SIST 1 registers (in any or-
der), insert a delay equivalent to 12 CLK periods
between the reads to ensure that the interrupts clear
properly. See Chapter 2, “Functional Description,”
for more information on interrupts.
Bit 7
DFE (DMA FIFO E mpty)
T his status bit is set when the DMA FIFO is
empty. It may be used to determine if any data
resides in the FIFO when an error occurs and
an interrupt is generated. T his bit is a pure sta-
tus bit and will not cause an interrupt.
Bit 6
MDPE (Master Data Parity E rror)
T his bit is set when the SYM53C875 as a mas-
ter detects a data parity error, or a target device
signals a parity error during a data phase. T his
bit is completely disabled by the Master Parity
Error Enable bit (bit 3 of CT EST 4).
Bit 5
BF (Bus Fault)
T his bit is set when a PCI bus fault condition
is detected. A PCI bus fault can only occur
when the SYM53C875 is bus master, and is
defined as a cycle that ends with a Bad Address
or Target Abort Condition.
Bit 4
ABRT (Aborted)
T his bit is set when an abort condition occurs.
An abort condition occurs when a software
abort command is issued by setting bit 7 of the
ISTAT register.
Bit 3
SSI (Single Step Interrupt)
If the Single-Step Mode bit in the DCNT L
register is set, this bit will be set and an inter-
rupt generated after successful execution of
each SCRIPT S instruction.
Bit 2
SIR (SCRIPT S Interrupt
Instruction Received)
T his status bit is set whenever an Interrupt
instruction is evaluated as true.
Bit 1
E BPI (E xtended Byte Parity E rror
Interrupt) (53C875N only)
T his bit is set whenever the SYM53C875
detects a parity error on one of the four addi-
tional parity pins on the SYM53C875N.
Bit 0
IID (Illegal Instruction Detected)
T his status bit will be set any time an illegal or
reserved instruction op code is detected,
whether the SYM53C875 is operating in
single-step mode or automatically executing
SCSI SCRIPT S. Any of the following condi-
tions during instruction execution will also
cause this bit to be set:
1. T he SYM53C875 is executing a Wait
Disconnect instruction and the SCSI REQ
line is asserted without a disconnect
occurring.
2. A Block Move instruction is executed with
000000h loaded into the DBC register,
indicating that zero bytes are to be moved.
3. During a Transfer Control instruction, the
Compare Data (bit 18) and Compare
Phase (bit 17) bits are set in the DBC
register while the SYM53C875 is in target
mode.
DFE
7
MDPE
6
BF
5
ABRT
4
SSI
3
SIR
2
RES
1
IID
0
Default>>>
1
0
0
0
0
0
X
0
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