參數(shù)資料
型號(hào)： SYM53C875E
廠商： LSI Corporation
英文描述： PCI-Ultra SCSI I/O Processor(PCI-Ultra SCSI I/O 處理器)
中文描述： 的PCI -超的SCSI I / O處理器（個(gè)PCI -超的SCSI的I / O處理器）
文件頁(yè)數(shù)： 56/243頁(yè)
文件大小： 1362K
代理商： SYM53C875E
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PCI Functional Description
Configuration Registers
3-6
SYM53C875/875E Data Manual
a Read Multiple command will be issued on all
read cycles, except op code fetches, when the fol-
lowing conditions have been met:
1. T he CLSE and ERMP bits must be set.
2. T he Cache Line Size register must contain a
legal burst size value (2, 4, 8, 16, 32, 64, or
128) AND that value must be less than or
equal to the DMODE burst size.
3. T he number of bytes to be transferred at the
time a cache boundary has been reached must
be at least twice the full cache line size.
4. T he chip must be aligned to a cache line
boundary.
When these conditions have been met, the chip
will issue a Read Multiple command instead of a
Memory Read during all PCI read cycles.
Burst Size Selection
T he Read Multiple command reads in multiple
cache lines of data in a single bus ownership. T he
number of cache lines to be read is a multiple of
the cache line size as allowed for in the Revision
2.1 of the PCI specification. T he logic will select
the largest multiple of the cache line size based on
the amount of data to transfer, with the maximum
allowable burst size being determined from the
DMODE Burst Size bits and CT EST 5, bit 2.
Read Multiple with Read Line E nabled
When both the Read Multiple and Read Line
modes have been enabled, the Read Line com-
mand will not be issued if the above conditions are
met. Instead, a Read Multiple command will be
issued, even though the conditions for Read Line
have been met.
If the Read Multiple mode is enabled and the Read
Line mode has been disabled, Read Multiple com-
mands will still be issued if the Read Multiple con-
ditions are met.
Unsupported PCI Commands
T he SYM53C875 does not respond to reserved
commands, special cycle, dual address cycle, or
interrupt acknowledge commands as a slave. It will
never generate these commands as a master.
Configuration Registers
T he Configuration registers are accessible only by
the system BIOS during PCI configuration cycles.
T he lower 128 bytes hold configuration data while
the upper 128 bytes hold the SYM53C875 operat-
ng registers, which are described in Chapter Five,
“Operating Registers.” T hese registers can be
accessed by SCRIPT S or the host processor, if
necessary.
Note: T he configuration register descriptions
provide general information only, to
indicate which PCI configuration addresses
are supported in the SYM53C875. For
detailed information, refer to the PCI
Specification.
Figure 3-1 shows the PCI configuration registers
implemented by the SYM53C875/875E.
All PCI-compliant devices, such as the
SYM53C875, must support the Vendor ID, Device
ID, Command, and Status Registers. Support of
other PCI-compliant registers is optional. In the
SYM53C875, registers that are not supported are
not writable and will return all zeroes when read.
Only those registers and bits that are currently
supported by the SYM53C875 are described in
this chapter. For more detailed information on
PCI registers, please see the PCI Specification.
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