參數(shù)資料
型號(hào): SX8652IWLTRT
廠商: Semtech
文件頁數(shù): 3/29頁
文件大?。?/td> 0K
描述: IC TOUCH SCREEN CTRLR 14DFN
標(biāo)準(zhǔn)包裝: 1
類型: 電阻
觸摸面板接口: 4 線,5 線
輸入數(shù)/鍵: 2
分辨率(位): 12 b
數(shù)據(jù)接口: 串行,SPI?
數(shù)據(jù)速率/采樣率 (SPS,BPS): 74k
電壓基準(zhǔn): 內(nèi)部
電源電壓: 1.65 V ~ 3.7 V
電流 - 電源: 10mA
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 14-WFDFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 14-DFN
包裝: 標(biāo)準(zhǔn)包裝
其它名稱: SX8652IWLDKR
Revision V1.7/October 2010
2010 Semtech Corp.
SX8652
www.semtech.com
Page 11
ADVANCED COMMUNICATIONS & SENSING
DATASHEET
15kV ESD Low Power 4-Wire / 5-Wire Resistive
Touchscreen Controller with SPI Interface
3.2. Device Interface and ESD protection
The touch screen controller inputs have been specially designed to provide robust on-chip ESD protection of up to ±15kV
in both HBM and Contact Discharge.
3.2.1. Touchscreen interface
The X+/BR, X-/TL, Y+/TR,Y-/BL, AUX/WIPER are the pins dedicated for the touchscreen interface. It provides the voltage
sequence in order to obtain the coordinates and pressure measurement.
The five pins are connected to BR, TL, TR, BL, WIPER on a 5-wire touchscreen. They are the electrodes on the 4 corners
of the bottom layer of the touchscreen plus the electrode on the top layer.
On a 4-wire touchscreen, only 4 electrodes are used: X+,X-,Y+,Y-. The AUX pin is not needed and therefore can be used
to convert an analog signal (range GND - VDD) into 12-bit digital value. The touchscreen interface pins are the most
exposed pins for an ESD event.
As shown in Figure 7, theses pins have internal ESD protection to GROUND and VDD.
3.2.2. Host Interface and Control Pins
The SX8652 is a slave device configured via the SPI interface.
NIRQ provides an interrupt to the host processor when a pen is detected or when channel data is available. The NIRQ pin
is an active low, open drain output to facilitate interfacing to different supply voltages and thus requires an external pull-up
resistor (1-10 kOhm).
The host can reset the chip via the SPI interface or with the dedicated pin NRST. The NRST pin is an active low input that
provides a hardware reset. An internal pull-up enables the interfacing with devices at different supply voltage.
NRST and NIRQ pins are protected to GROUND.
Figure 7. ESD protection
T o u c h
S c r e e n
D r i v e r s
I n t e r f a c e
R c h n
A
D
C
C o n t r o l
D a t a P r o c e s s in g
X + / B R
X - / T L
Y + / T R
Y - / B L
A U X /
W i p e r
M U X
R c h n
P o w e r
M a n a g e m e n t
V D D
G N D
N R S T
N I R Q
S P I
N
C
S
C
L
K
D
O
U
T
D
IN
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