參數(shù)資料
型號: STR751FR0
廠商: 意法半導(dǎo)體
元件分類: ADC
英文描述: Zener Diode; Application: General; Pd (mW): 400; Vz (V): 29.02 to 30.51; Condition Iz at Vz (mA): 5; C (pF) max: -; Condition VR at C (V):   ESD (kV) min: -; Package: MHD
中文描述: 的ARM7TDMI - S⑩32位微控制器的閃存,新措施,3性病16位定時器,PWM定時器,快速的10位ADC和I2C,UART的,過磷酸鈣,USB和CAN
文件頁數(shù): 44/84頁
文件大?。?/td> 997K
代理商: STR751FR0
STR750Fxx STR751Fxx STR752Fxx STR755Fxx
Electrical parameters
49/84
PLL characteristics
Subject to general operating conditions for VDD_IO, and TA.
Internal RC oscillators (FREEOSC & LPOSC)
Subject to general operating conditions for VDD_IO, and TA.
Table 24.
PLL characteristics
Symbol
Parameter
Test Conditions
Value
Unit
Min
Typ
Max(1)
1.
Data based on product characterisation, not tested in production.
fPLL_IN
PLL input clock
4.0
MHz
PLL input clock duty cycle
40
60
%
fPLL_OUT
PLL multiplier output clock
fPLL_INx 24
165
MHz
fVCO
VCO frequency range
When PLL
operates (locked)
336
960
MHz
tLOCK
PLL lock time
300
s
tJITTER1(2)(3)
2.
Refer to jitter terminology in : PLL characteristics on page 47 for details on how jitter is specified.
3.
The jitter specification holds true only up to 50mV (peak-to-peak) noise on VDDA_PLL and V18 supplies.
Jitter will increase if the noise is more than 50mV. In addition, it assumes that the input clock has no jitter.
Single period jitter (+/-3
Σ peak
to peak)
fPLL_IN = 4 MHz
(4)
VDD_IO is stable
4.
The PLL parameters (MX1, MX0, PRESC1, PRESC2) must respect the constraints described in: PLL
characteristics on page 47.
+/-250
ps
tJITTER2(2)(3)
Long term jitter (+/-3
Σ peak to
peak)
fPLL_IN = 4 MHz
(4)
VDD_IO is stable
+/-2.5
ns
tJITTER3(2)(3)
Cycle to cycle jitter (+/-3
Σ peak
to peak)
fPLL_IN = 4 MHz
(4)
VDD_IO is stable
+/-500
ps
Table 25.
Internal RC oscillators (FREEOSC & LPOSC)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fCK_FREEOSC FREEOSC Oscillator Frequency
3
5
8
MHz
fCK_LPOSC
LPOSC Oscillator Frequency
150
300
500
kHz
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