參數(shù)資料
型號: STR751FR0
廠商: 意法半導(dǎo)體
元件分類: ADC
英文描述: Zener Diode; Application: General; Pd (mW): 400; Vz (V): 29.02 to 30.51; Condition Iz at Vz (mA): 5; C (pF) max: -; Condition VR at C (V):   ESD (kV) min: -; Package: MHD
中文描述: 的ARM7TDMI - S⑩32位微控制器的閃存,新措施,3性病16位定時(shí)器,PWM定時(shí)器,快速的10位ADC和I2C,UART的,過磷酸鈣,USB和CAN
文件頁數(shù): 36/84頁
文件大?。?/td> 997K
代理商: STR751FR0
STR750Fxx STR751Fxx STR752Fxx STR755Fxx
Electrical parameters
41/84
Subject to general operating conditions for VDD_IO, and TA
Table 16.
Dual supply supply typical power consumption in Run, WFI, Slow and
Slow-WFI modes
To calculate the power consumption in Dual supply mode, refer to the values given in Table 15. and
consider that this consumption is split as follows:
IDD(single supply)~IDD(dual supply)= IDD_V18 + IDD(VDD_IO)
For 3.3V range: IDD(VDD_IO) ~ 1 to 2 mA
For 5V range: IDD(VDD_IO) ~ 2 to 3 mA
Therefore most of the consumption is sunk on the V18 power supply
This formula does not apply in STOP and STANDBY modes, refer to Table 17.
Table 17.
Typical power consumption in STOP and STANDBY modes
Symbol
Parameter
Conditions
3.3V
Typ(1)
5V
Typ(2)
Unit
IDD
(3)
Supply current
in STOP
mode(4)
LP_PARAM bits: ALL OFF(5)
12
15
A
LP_PARAM bits : MVREG ON, OSC4M OFF, FLASH
OFF(6)
130
135
LP_PARAM bits: MVREG ON, OSC4M ON , FLASH
OFF(6)
1950
1930
LP_PARAM bits: MVREG ON, OSC4M OFF, FLASH ON (6)
630
635
LP_PARAM bits: MVREG ON, OSC4M ON, FLASH ON (6)
2435
2425
Supply current
in STOP
mode(7)
LPPARAM bits: ALL OFF, with V18=1.8 V
IDD_V18
IDD_V33
5
<1
5
<1
A
LP_PARAM bits: OSC4M ON, FLASH OFF
IDD_V18
IDD_V33
410
1475
410
1435
LP_PARAM bits: OSC4M OFF, FLASH ON
IDD_V18
IDD_V33
550
<1
550
1
LP_PARAM bits: OSC4M ON, FLASH ON
IDD_V18
IDD_V33
910
1475
910
1445
Supply current
in STANDBY
mode(4)
RTC OFF
11
14
A
RTC ON clocked by OSC32K
14
18
1.
Typical data are based on TA=25°C, VDD_IO=3.3 V and V18=1.8 V unless otherwise indicated in the table.
2.
Typical data are based on TA=25°C, VDD_IO=5.0 V and V18=1.8 V unless otherwise indicated in the table.
3.
The conditions for these consumption measurements are described at the beginning of Section 5.3.4 on page 36.
4.
Single supply scheme see Figure 12.
5.
In this mode, the whole digital circuitry is powered internally by the LPVREG at approximately 1.4 V, which significantly
reduces the leakage currents.
6.
In this mode, the whole digital circuitry is powered internally by the MVREG at 1.8 V.
7.
Dual supply scheme see Figure 13.
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