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參數(shù)資料
| 型號： | STM1404CRNCQ6F |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 電源管理 |
| 英文描述： | 1-CHANNEL POWER SUPPLY SUPPORT CKT, QCC16 |
| 封裝： | 3 X 3 MM, ROHS COMPLIANT, QFN-16 |
| 文件頁數(shù)： | 21/35頁 |
| 文件大?。?/td> | 366K |
| 代理商： | STM1404CRNCQ6F |
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DC and AC parameters
STM1404
Reset thresholds
VRST
(9)
Reset threshold
T
VCC falling
3.00
3.075
3.15
V
VCC rising
3.00
3.085
3.17
V
S
VCC falling
2.85
2.925
3.00
V
VCC rising
2.85
2.935
3.02
V
R
VCC falling
2.55
2.625
2.70
V
VCC rising
2.55
2.635
2.72
V
trec
RST pulse width
140
200
280
ms
Push-button reset input
tMLMH
tMR
MR pulse width
100
ns
tMLRL
tMRD
MR to RST output
delay
60
500
ns
1.
Valid for ambient operating temperature: TA = –40 to 85°C; VCC = VRST (max) to 3.6 V; and VBAT = 2.8 V (except where
noted); typical values are for 3.3 V and 25°C.
2.
VCC supply current, logic input leakage, push-button reset functionality, PFI functionality, state of RST tested at
VBAT = 3.6 V, and VCC = 3.6 V. The state of RST and PFO is tested at VCC = VCC (min). VBAT is voltage measured at the
pin.
3.
Tested at VBAT = 3.6 V, and VCC = 0 V.
4.
Guaranteed by design.
5.
The leakage current measured on the RST, SAL, PFO, and BLD pins are tested with the output not asserted (output high
impedance).
6.
When VBAT > VCC > VSW, VOUT remains connected to VCC until VCC drops below VSW.
7.
When VSW > VCC > VBAT, VOUT remains connected to VCC until VCC drops below the battery voltage (VBAT) – 75 mV.
8.
Maximum external capacitive load on VREF pin cannot exceed 1 nF.
9.
The reset threshold tolerance is wider for VCC rising than for VCC falling due to the 10 mV (typ) hysteresis, which prevents
internal oscillation.
Table 6.
DC and AC characteristics (continued)
Sym
Alter-
native
Description
Test condition(1)
Min
Typ
Max
Unit
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