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參數(shù)資料
| 型號： | STLC2411 |
| 廠商： | 意法半導體 |
| 英文描述： | BLUETOOTH BASEBAND |
| 中文描述： | 藍牙基帶 |
| 文件頁數(shù)： | 20/25頁 |
| 文件大?。?/td> | 216K |
| 代理商： | STLC2411 |
STLC2411
20/25
interface is programmable to be CVSD, A-Law or μ-Law.
The PCM block is able to manage the PCM bus with up to 3 timeslots.
PCM clock and data are in master mode available at 2 MHz or at 2.048 MHz to allow interfacing of stan-
dard codecs.
The four signals of the PCM interface are:
– PCM_CLK :
PCM clock
– PCM_SYNC :
PCM 8kHz sync
– PCM_A :
PCM data
– PCM_B :
PCM data
Directions of PCM_A and PCM_B are software configurable.
Three additional PCM_SYNC signals can be provided via the GPIOs. See section 12 for more details.
Figure 9. PCM (A-law,
μ
-law) standard mode
Figure 10. Linear mode
Table 13. PCM interface timing.
Symbol
PCM Interface
F
pcm_clk
F
pcm_sync
t
WCH
t
WCL
t
WSH
t
SSC
t
SDC
t
HCD
t
DCD
Description
Min
Typ
Max
Unit
Frequency of PCM_CLK (master)
Frequency of PCM_SYNC
2048
8
kHz
kHz
High period of PCM_CLK
200
ns
Low period of PCM_CLK
High period of PCM_SYNC
200
200
ns
ns
Setup time, PCM_SYNC high to PCM_CLK low
100
ns
Setup time, PCM_A/B input valid to PCM_CLK low
Hold time, PCM_CLK low to PCM_A/B input invalid
100
100
ns
ns
Delay time, PCM_CLK high to PCM_A/B output valid
150
ns
D02TL558
PCM_CLK
PCM_SYNC
PCM_A
B
B
PCM_B
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
B
125
μ
s
B
D02TL559
PCM_CLK
PCM_SYNC
PCM_A
PCM_B
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
125
μ
s
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