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參數(shù)資料
| 型號： | STE26N50 |
| 廠商： | 意法半導體 |
| 英文描述： | N - CHANNEL ENHANCEMENT MODE POWER MOS TRANSISTOR IN ISOTOP PACKAGE |
| 中文描述： | ? -通道增強型功率MOS器件中的ISOTOP封裝 |
| 文件頁數(shù)： | 1/8頁 |
| 文件大?。?/td> | 154K |
| 代理商： | STE26N50 |
STE26N50
N - CHANNEL ENHANCEMENT MODE
POWER MOS TRANSISTOR IN ISOTOP PACKAGE
I
HIGH CURRENT POWER MODULE
I
AVALANCHE RUGGED TECHNOLOGY
(SEE IRFP450 FOR RATING)
I
VERY LARGE SOA - LARGE PEAK POWER
CAPABILITY
I
EASY TO MOUNT
I
SAME CURRENT CAPABILITY FOR THE
TWO SOURCE TERMINALS
I
EXTREMELY LOW R
th
JUNCTION TO CASE
I
VERY LOW DRAIN TO CASE CAPACITANCE
I
VERY LOW INTERNAL PARASITIC
INDUCTANCE (TYPICALLY < 5 nH)
I
ISOLATED PACKAGE UL RECOGNIZED
(FILE No E81743)
INDUSTRIAL APPLICATIONS:
I
SMPS & UPS
I
MOTOR CONTROL
I
WELDING EQUIPMENT
I
OUTPUT STAGE FOR PWM,ULTRASONIC
CIRCUITS
July 1993
TYPE
V
DSS
R
DS(on)
< 0.2
I
D
STE26N50
500 V
26 A
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V
DS
Drain-Source Voltage (V
GS
= 0)
Drain-Gate Voltage (R
GS
= 20 k
)
Gate-Source Voltage
Drain Current (continuous) at T
c
= 25
o
C
Drain Current (continuous) at T
c
= 100
o
C
500
V
V
DGR
500
±
20
26
V
V
GS
V
I
D
A
I
D
17
A
I
DM
(
)
P
tot
Drain Current (pulsed)
Total Dissipation at T
c
= 25
o
C
104
A
300
W
Derating Factor
2.4
W/
o
C
o
C
o
C
T
stg
Storage Temperature
-55 to 150
T
j
Max. Operating Junction Temperature
150
V
ISO
Insulation Withstand Voltage (AC-RMS)
(
) Pulse width limited by safe operating area
2500
V
3
2
1
4
INTERNAL SCHEMATIC DIAGRAM
ISOTOP
1/8
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