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Introduction
1.4 Product Family
Samsung ASIC
1-9
STD150
1.4.3 COMPILED MEMORY
Today’s System-On-Chip (SoC) designs require various configurations of
embedded memories. These configurations must be optimized for each process
and also optimized for speed, density, and power consumption. Samsung’s
memory compiler, called CubicCompiler, is designed under the efficiency of
custom memory design to achieve optimal designs. Using CubicCompiler is
helpful for designers to perform optimal floorplanning of the design because
designers can evaluate architectural tradeoffs between performance, area and
power by easily varying the aspect ratios, word depths and word widths of their
designs.
Once satisfied with the resulting configuration, CubicCompiler allows designers
toeasilygeneratecompleteEDAmodelsincludingfunctionalmodel,timingmodel
and physical layout. There are two memory families in STD150, high-density
compiled memories and low-power compiled memories. The high-density
memories are fully optimized for the smallest area and are targeted for high-
integration applications. The low-power memories are fully optimized for lowest
power consumption and are targeted for low-power applications. Memories in
STD150 are fully user-configurable and are provided as a compiler as follows:
High-Density Compiled Memories
- Single-port synchronous SRAM
- Single-port synchronous SRAM with bit-write
- Single-port synchronous SRAM with redundancy
- Dual-port synchronous SRAM
- Dual-port synchronous SRAM with bit-write
- Dual-post Synchronous SRAM with redundancy
- Multi-port synchronous register file
- Multi-port synchronous register file with bit-write
- Single-port synchronous via-1 programmable ROM
- Single-port Synchronous Binary CAM
- Single-port Synchronous Ternary CAM
- Synchronous First-In First-Out Memory (On-demand)
- High-capacity (Up to 4Mbits) single-port synchronous SRAM with burst
operations (On-demand)
- High-capacity (Up to 4Mbits) single-port synchronous via-1 programmable
ROM (On-demand)
Low-Power Compiled Memories
- Single-port synchronous static RAM
- Single-port synchronous static RAM with bit-write
- Single-port synchronous static RAM with redundancy
- Dual-port synchronous static RAM
- Dual-port synchronous static RAM with bit-write
- Dual-port Synchronous SRAM with redundancy
STD150 compiled memory families adopt most advanced memory design
techniques such as self-controlled timing circuits, partial activation architecture,
multi-stage low power decoding structure and high-sensitivity sense amplifiers
with high stability, to dramatically improve the performance and reduce power
consumption. Such circuits are extensively optimized for the specified voltage,
temperature and process and give designers high performance and high stability.