
Samsung ASIC
5-193
STD130
DPSRAM_LP
Low-Power Dual-Port Synchronous Static RAM
Logic Symbol
Function Description
DPSRAM_LP is a dual-port synchronous static RAM which is provided as a compiler. DPSRAM_LP is
intended for use in low-power applications. Each port is fully independent. On the rising edge of CK1 (CK2),
the write cycle is initiated when WEN1 (WEN2) is low and CSN1 (CSN2) is low. The data on DI1[] (DI2[]) is
written into the memory location specified on A1[](A2[]). During the write cycle, DOUT1[] (DOUT2[]) remains
stable. On the rising edge of CK1 (CK2), the read cycle is initiated when WEN1 (WEN2) is high and
CSN1(CSN2) is low. The data at DOUT1[] (DOUT2[]) become valid after a delay. While in standby mode that
CSN1(CSN2) is high, A1[] (A2[]) and DI1[] (DI2[]) are disabled, data stored in the memory is retained and
DOUT1[] (DOUT2[]) remains stable. When OEN1 (OEN2) is high, DOUT1[] (DOUT2[]) is placed in a
high-impedance state.
DPSRAM_LP Function Table
CK1
CK2
X
X
↑
↑
CSN1
CSN2
X
H
L
L
WEN1
WEN2
X
X
L
H
OEN1
OEN2
H
L
L
L
A1
A2
X
X
Valid
Valid
DI1
DI2
X
X
Valid
X
DOUT1
DOUT2
Z
DOUT(t-1)
DOUT(t-1)
MEM(A)
Comment
Unconditional tri-state output
De-selected (standby mode)
Write cycle
Read cycle
Features
Suitable for low-power application
Separated data I/O
Synchronous operation
Duty-free clock cycle
Asynchronous tri-state output control
Latched inputs and outputs
Automatic power-down
Zero standby current
Zero hold time
Low noise output optimization
Flexible aspect ratio
Up to 256K bits capacity
Up to 16K number of words
Up to 128 number of bit per word
NOTES:
1. Words (w) is the number of words.
2. Bpw (b) is the number of bits per word.
3. Ymux (y) is one of the column mux types.
4. m =
log
2
w
CK1
CK2
CSN1
CSN2
WEN1
WEN2
OEN1
OEN2
A1 [m-1:0]
A2 [m-1:0]
DI1 [b-1:0]
DI2 [b-1:0]
dpsram_lp_<w>x<b>m<y>
DOUT1 [b-1:0]
DOUT2 [b-1:0]