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| 型號(hào)： | ST7PLU05MAE |
| 廠商： | STMICROELECTRONICS |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDSO8 |
| 封裝： | 0.150 INCH, ROHS COMPLIANT, PLASTIC, SOP-8 |
| 文件頁(yè)數(shù)： | 73/124頁(yè) |
| 文件大小： | 1995K |
| 代理商： | ST7PLU05MAE |
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Power saving modes
ST7LUS5, ST7LU05, ST7LU09
To compensate for any frequency dispersion of the AWU RC oscillator, it can be calibrated
by measuring the clock frequency fAWU_RC and then calculating the right prescaler value.
Measurement mode is enabled by setting the AWUM bit in the AWUCSR register in Run
mode. This connects fAWU_RC to the input capture of the 8-bit lite timer, allowing the
fAWU_RC to be measured using the main oscillator clock as a reference timebase.
The following AWUFH mode behavior is the same as normal Halt mode:
●
The MCU can exit AWUFH mode by means of any interrupt with exit from Halt
capability or a reset (see Section 8.4: Active Halt and Halt modes).
●
When entering AWUFH mode, the I bit in the CC register is forced to 0 to enable
interrupts. Therefore, if an interrupt is pending, the MCU wakes up immediately.
●
In AWUFH mode, the main oscillator is turned off causing all internal processing to be
stopped, including the operation of the on-chip peripherals. None of the peripherals are
clocked except those which get their clock supply from another clock generator (such
as an external or auxiliary oscillator like the AWU oscillator).
●
The compatibility of watchdog operation with AWUFH mode is configured by the
WDGHALT option bit in the option byte. Depending on this setting, the HALT instruction
when executed while the watchdog system is enabled, can generate a watchdog
RESET.
Figure 24.
AWUF Halt timing diagram
AWUFH interrupt
fCPU
RUN MODE
HALT MODE
64 tCPU
RUN MODE
fAWU_RC
Clear
by software
tAWU
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