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參數(shù)資料
| 型號(hào)： | ST7PLU05MAE |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDSO8 |
| 封裝： | 0.150 INCH, ROHS COMPLIANT, PLASTIC, SOP-8 |
| 文件頁數(shù)： | 67/124頁 |
| 文件大?。?/td> | 1995K |
| 代理商： | ST7PLU05MAE |
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ST7LUS5, ST7LU05, ST7LU09
Power saving modes
47/124
8.4.1
Active Halt mode
Active Halt mode is the lowest power consumption mode of the MCU with a real-time clock
available. It is entered by executing the ‘HALT’ instruction when active halt mode is enabled.
The MCU can exit Active Halt mode on reception of a Lite Timer / AT Timer interrupt or a
RESET.
●
When exiting Active Halt mode by means of a RESET, a 64 CPU cycle delay occurs.
After the start up delay, the CPU resumes operation by fetching the reset vector which
woke it up (see Figure 20).
●
When exiting Active Halt mode by means of an interrupt, the CPU immediately
resumes operation by servicing the interrupt vector which woke it up (see Figure 20).
When entering Active Halt mode, the I bit in the CC register is cleared to enable interrupts.
Therefore, if an interrupt is pending, the MCU wakes up immediately.
In Active Halt mode, only the main oscillator and the selected timer counter (LT/AT) are
running to keep a wake-up time base. All other peripherals are not clocked except those
which get their clock supply from another clock generator (such as external or auxiliary
oscillator).
Caution:
As soon as Active Halt is enabled, executing a HALT instruction while the Watchdog is active
does not generate a RESET if the WDGHALT bit is reset. This means that the device cannot
spend more than a defined delay in this power saving mode.
Figure 19.
Active Halt timing overview
1.
This delay occurs only if the MCU exits Active Halt mode by means of a RESET.
HALT
RUN
64 CPU
CYCLE DELAY(1)
RESET
OR
INTERRUPT
HALT
INSTRUCTION
FETCH
VECTOR
ACTIVE
[Active Halt Enabled]
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