參數(shù)資料
型號： ST7PLU05MAE
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDSO8
封裝： 0.150 INCH, ROHS COMPLIANT, PLASTIC, SOP-8
文件頁數(shù)： 53/124頁
文件大?。?/td> 1995K
代理商： ST7PLU05MAE
Supply, reset and clock management
ST7LUS5, ST7LU05, ST7LU09
6.3.2
Asynchronous external RESET pin
The RESET pin is both an input and an open-drain output with integrated RON weak pull-up
resistor. This pull-up has no fixed value but varies in accordance with the input voltage. It
can be pulled low by external circuitry to reset the device. See Chapter 12: Electrical
characteristics for more details.
A RESET signal originating from an external source must have a duration of at least
th(RSTL)in in order to be recognized (see Figure 12). This detection is asynchronous and
therefore the MCU can enter reset state even in Halt mode.
The RESET pin is an asynchronous signal which plays a major role in EMS performance. In
a noisy environment, it is recommended to follow the guidelines mentioned in Chapter 12:
6.3.3
External power-on RESET
If the LVD is disabled by the option byte, to start up the microcontroller correctly, the user
must ensure by means of an external reset circuit that the reset signal is held low until VDD
is over the minimum level specified for the selected fCLKIN frequency.
A proper reset signal for a slow rising VDD supply can generally be provided by an external
RC network connected to the RESET pin.
6.3.4
Internal low voltage detector (LVD) RESET
Two different RESET sequences caused by the internal LVD circuitry can be distinguished:
●
Power-On RESET
●
Voltage Drop RESET
The device RESET pin acts as an output that is pulled low when VDD <VIT+ (rising edge) or
VDD <VIT- (falling edge) as shown in Figure 12.
The LVD filters spikes on VDD larger than tg(VDD) to avoid parasitic resets.
6.3.5
Internal watchdog RESET
The RESET sequence generated by a internal Watchdog counter overflow is shown in
Starting from the Watchdog counter underflow, the device RESET pin acts as an output that
is pulled low during at least tw(RSTL)out.
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