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參數(shù)資料
| 型號： | ST7PLITE05Y0M3 |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PDSO16 |
| 封裝： | 0.150 INCH, PLASTIC, SOP-16 |
| 文件頁數(shù)： | 33/115頁 |
| 文件大?。?/td> | 781K |
| 代理商： | ST7PLITE05Y0M3 |
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ST7FLITE0
24/115
7.4 RESET SEQUENCE MANAGER (RSM)
7.4.1 Introduction
The reset sequence manager includes three RE-
SET sources as shown in Figure 14:
s
External RESET source pulse
s
Internal LVD RESET (Low Voltage Detection)
s
Internal WATCHDOG RESET
These sources act on the RESET pin and it is al-
ways kept low during the active phase.
The RESET service routine vector is fixed at ad-
dresses FFFEh-FFFFh in the ST7 memory map.
The basic RESET sequence consists of 3 phases
as shown in Figure 13:
s
Active phase depending on the RESET source
s
256 CPU clock cycle delay
s
RESET vector fetch
The 256 CPU clock cycle delay allows the oscilla-
tor to stabilise and ensures that recovery has tak-
en place from the Reset state.
The RESET vector fetch phase duration is 2 clock
cycles.
Figure 13. RESET Sequence Phases
Note: Whatever the reset source is (internal or ex-
ternal), the user must ensure that the level on the
RESET pin can go below the VIL max. level speci-
fied in section 13.9.1 on page 99 . Otherwise the
reset will not be taken into account internally.
Caution: Because the reset circuit is designed to
allow an internal RESET to act on the RESET pin,
the user must ensure that the current sunk on the
RESET pin (by an external pull-up for example) is
less than the absolute maximum value specified
for IINJ(RESET) in section 13.2.2 on page 78.
Figure 14. Reset Block Diagram
RESET
ACTIVE PHASE
INTERNAL RESET
256 CLOCK CYCLES
FETCH
VECTOR
RESET
RON
VDD
WATCHDOG RESET
LVD RESET
INTERNAL
RESET
PULSE
GENERATOR
FILTER
1
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