參數(shù)資料
型號: ST7PLITE05Y0M3
廠商: STMICROELECTRONICS
元件分類: 微控制器/微處理器
英文描述: 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PDSO16
封裝: 0.150 INCH, PLASTIC, SOP-16
文件頁數(shù): 24/115頁
文件大?。?/td> 781K
代理商: ST7PLITE05Y0M3
ST7FLITE0
16/115
DATA EEPROM (Cont’d)
5.4 POWER SAVING MODES
Wait mode
The DATA EEPROM can enter WAIT mode on ex-
ecution of the WFI instruction of the microcontrol-
ler. The DATA EEPROM will immediately enter
this mode if there is no programming in progress,
otherwise the DATA EEPROM will finish the cycle
and then enter WAIT mode.
Halt mode
The DATA EEPROM immediately enters HALT
mode if the microcontroller executes the HALT in-
struction. Therefore the EEPROM will stop the
function in progress, and data may be corrupted.
5.5 ACCESS ERROR HANDLING
If a read access occurs while E2LAT=1, then the
data bus will not be driven.
If a write access occurs while E2LAT=0, then the
data on the bus will not be latched.
If a programming cycle is interrupted (by software/
RESET action), the memory data will not be guar-
anteed.
5.6 Data EEPROM Read-out Protection
The read-out protection is enabled through an op-
tion bit (see section 15.1 on page 108).
When this option is selected, the programs and
data stored in the EEPROM memory are protected
against read-out piracy (including a re-write pro-
tection). In Flash devices, when this protection is
removed by reprogramming the Option Byte, the
entire Program memeory and EEPROM is first au-
tomatically erased.
Note: Both Program Memory and data EEPROM
are protected using the same option bit.
Figure 8. Data EEPROM Programming Cycle
LAT
ERASE CYCLE
WRITE CYCLE
PGM
tPROG
READ OPERATION NOT POSSIBLE
WRITE OF
DATA LATCHES
READ OPERATION POSSIBLE
INTERNAL
PROGRAMMING
VOLTAGE
1
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