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參數(shù)資料
| 型號： | ST7FLITE09Y0B3 |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PDIP16 |
| 封裝： | 0.300 INCH, PLASTIC, DIP-16 |
| 文件頁數(shù)： | 62/115頁 |
| 文件大?。?/td> | 781K |
| 代理商： | ST7FLITE09Y0B3 |
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ST7FLITE0
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12-BIT AUTORELOAD TIMER (Cont’d)
11.2.3 Functional Description
PWM Mode
This mode allows a Pulse Width Modulated sig-
nals to be generated on the PWM0 output pin with
minimum core processing overhead. The PWM0
output signal can be enabled or disabled using the
OE0 bit in the PWMCR register. When this bit is
set the PWM I/O pin is configured as output push-
pull alternate function.
Note: CMPF0 is available in PWM mode (see
PWM0CSR description on page 53).
PWM Frequency and Duty Cycle
The PWM signal frequency (fPWM) is controlled by
the counter period and the ATR register value.
fPWM =fCOUNTER / (4096 - ATR)
Following the above formula, if fCPU is 8 MHz, the
maximum value of fPWM is 4 Mhz (ATR register
value = 4094), and the minimum value is 2 kHz
(ATR register value = 0).
Note: The maximum value of ATR is 4094 be-
cause it must be lower than the DCR value which
must be 4095 in this case.
At reset, the counter starts counting from 0.
Software must write the duty cycle value in the
DCR0H and DCR0L preload registers. The
DCR0H register must be written first. See caution
below.
When a upcounter overflow occurs (OVF event),
the ATR value is loaded in the upcounter, the
preloaded Duty cycle value is transferred to the
Duty Cycle register and the PWM0 signal is set to
a high level. When the upcounter matches the
DCRx value the PWM0 signals is set to a low level.
To obtain a signal on the PWM0 pin, the contents
of the DCR0 register must be greater than the con-
tents of the ATR register.
The polarity bit can be used to invert the output
signal.
The maximum available resolution for the PWM0
duty cycle is:
Resolution = 1 / (4096 - ATR)
Note: To get the maximum resolution (1/4096), the
ATR register must be 0. With this maximum reso-
lution and assuming that DCR=ATR,
a 0% or
100% duty cycle can be obtained by changing the
polarity .
Caution: As soon as the DCR0H is written, the
compare function is disabled and will start only
when the DCR0L value is written. If the DCR0H
write occurs just before the compare event, the
signal on the PWM output may not be set to a low
level. Consequently, the DCRx register should be
updated just after an OVF event.
Figure 33. PWM Function
DUTY CYCLE
REGISTER
AUTO-RELOAD
REGISTER
PWM0
OUTPUT
t
4095
000
WITH OE0=1
AND OP0=0
(ATR)
(DCR0)
WITH OE0=1
AND OP0=1
COUNTER
1
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ST7FLITE09Y0B6 | 功能描述:8位微控制器 -MCU Flash 1.5K SPI Intrf RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| ST7FLITE09Y0B6 | 制造商:STMicroelectronics 功能描述:IC 8BIT FLASH MCU 7FLITE09 DIP16 |
| ST7FLITE09Y0B6TR | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8-bit microcontroller with single voltage Flash memory, data EEPROM, ADC, timers, SPI |
| ST7FLITE09Y0M3 | 功能描述:8位微控制器 -MCU Flash 1.5K SPI Intrf RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| ST7FLITE09Y0M6 | 功能描述:8位微控制器 -MCU Flash 1.5K SPI Intrf RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
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