參數(shù)資料
型號: ST7FLITE09Y0B3
廠商: STMICROELECTRONICS
元件分類: 微控制器/微處理器
英文描述: 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PDIP16
封裝: 0.300 INCH, PLASTIC, DIP-16
文件頁數(shù): 115/115頁
文件大?。?/td> 781K
代理商: ST7FLITE09Y0B3
ST7FLITE0
99/115
13.9 CONTROL PIN CHARACTERISTICS
13.9.1 Asynchronous RESET Pin
TA = -40°C to 125°C, unless otherwise specified
Figure 84. Typical Application with RESET pin 6)7)8)
Notes:
1. Data based on characterization results, not tested in production.
2. The IIO current sunk must always respect the absolute maximum rating specified in Section 13.2.2 and the sum of IIO
(I/O ports and control pins) must not exceed IVSS.
3. The RON pull-up equivalent resistor is based on a resistive transistor. Specfied for voltages on RESET pin between
VILmax and VDD
4. To guarantee the reset of the device, a minimum pulse has to be applied to the RESET pin. All short pulses applied on
RESET pin with a duration below th(RSTL)in can be ignored.
5. The reset network protects the device against parasitic resets.
6. The output of the external reset circuit must have an open-drain output to drive the ST7 reset pad. Otherwise the device
can be damaged when the ST7 generates an internal reset (LVD or watchdog).
7. Whatever the reset source is (internal or external), the user must ensure that the level on the RESET pin can go below
the VIL max. level specified in section 13.9.1 on page 99 . Otherwise the reset will not be taken into account internally.
8. Because the reset circuit is designed to allow the internal RESET to be output in the RESET pin, the user must ensure
that the current sunk on the RESET pin (by an external pull-p for example) is less than the absolute maximum value spec-
ified for IINJ(RESET) in section 13.2.2 on page 78.
Symbol
Parameter
Conditio ns
Min
Typ
Max
Unit
VIL
Input low level voltage
0.3xVDD
V
VIH
Input high level voltage
0.7xVDD
Vhys
Schmitt trigger voltage hysteresis 1)
2V
VOL
Output low level voltage 2)
VDD=5V
IIO=+5mA TA≤85°C
TA≥85°C
0.5
1.0
1.2
V
IIO=+2mA TA≤85°C
TA≥85°C
0.2
0.4
0.5
RON
Pull-up equivalent resistor 3) 1)
VDD=5V
204080
k
VDD=3V.
TBD
tw(RSTL)out Generated reset pulse duration
External pin or
internal reset sources
30
s
th(RSTL)in External reset pulse hold time
4)
20
s
tg(RSTL)in Filtered glitch duration
5)
200
ns
RESET
VDD
WATCH DOG
ST72XXX
LVD
INTERNAL
RON
0.1
F
VDD
0.1
F
VDD
4.7k
EXTERNAL
RESE T
CIRCUIT 8)
RESET CONTROL
O
PT
IO
N
AL
USER
1
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