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參數(shù)資料
| 型號： | ST75C540FP-A |
| 廠商： | 意法半導體 |
| 英文描述： | SUPER INTEGRATED DEVICESWITH DSP, AFE & MEMORIES FORTELEPHONY,MODEM, FAXOVERINTERNET& POTSLINES |
| 中文描述： | 超級綜合DEVICESWITH數(shù)字信號處理器，模擬前端 |
| 文件頁數(shù)： | 61/84頁 |
| 文件大?。?/td> | 599K |
| 代理商： | ST75C540FP-A |
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X.3 - ReceiveBuffers
Symetrically two identical buffers are provided to
exchange
receive
ST75C530/540and the host processor. While the
ST75C530/540is fillingone of the bufferswith the
receivebits,thehostprocessorisreadingtheother
buffer. As soon as the hosthas emptied a bufferit
frees it by writing 0 in the buffer status byte.
data
between
the
The DUAL Ram area associated with the receive
buffersis as following table.
Name
Address
$1C
$1D
$1E
$1F
$20
$21
$22
$23
$24
$25
$26
$27
$28
$29
$2A
$2B
$2C
$2D
Description
DTRBS0
DTRBS0 [0]
DTRBS0 [1]
DTRBS0 [2]
DTRBS0 [3]
DTRBS0 [4]
DTRBS0 [5]
DTRBS0 [6]
DTRBS0 [7]
DTRBS1
DTRBS1 [0]
DTRBS1 [1]
DTRBS1 [2]
DTRBS1 [3]
DTRBS1 [4]
DTRBS1 [5]
DTRBS1 [6]
DTRBS1 [7]
Buffer 0 Status Byte
Buffer 0 Data Byte 0
Buffer 0 Data Byte 1
Buffer 0 Data Byte 2
Buffer 0 Data Byte 3
Buffer 0 Data Byte 4
Buffer 0 Data Byte 5
Buffer 0 Data Byte 6
Buffer 0 Data Byte 7
Buffer 1 Status Byte
Buffer 1 Data Byte 0
Buffer 1 Data Byte 1
Buffer 1 Data Byte 2
Buffer 1 Data Byte 3
Buffer 1 Data Byte 4
Buffer 1 Data Byte 5
Buffer 1 Data Byte 6
Buffer 1 Data Byte 7
The Bit 0 (LSB) of the Buffer 0 Data Byte 0 is the
firstreceived bit in time (the oldest).
Accordingto the Data Format,the Statusbyte of a
bufferhasdifferentmeaning.Howevera valueof 0
signalsto theST75C530/540thatabufferisempty.
This value is set by the Host each time it has
emptied the buffer. After having used one buffer,
the host must select the other buffer for the next
operation.The Host must startwith the Buffer0 as
soon as the
STA_109
signal goes.
A mechanism of interruption (
IT3
for Receive) is
associatedwiththe Data Buffermanagment.Each
time a bufferis filled by the ST75C530/540it gen-
eratesan interrupt.
X.4 - Interruption
Two Interrupt signals are provided in orderto syn-
chronize the Data Buffer Exchanges.
IT2
is asso-
ciatedwiththeTransmitBuffermechanismand
IT3
with the Receive Buffer mechanism.
In order to enable these interrupts, the Host proc-
essor must set the bit 2 (for
IT2
) and the bit 3 (for
IT3
) of the
ITMASK
Registerto 1. It must also set
the Bit 7 of the
ITMASK
register to 1 in order to
globallyenable alltheselectedsourcesof interrup-
tion.
When an Interruptoccurs(low level on
SINTR
pin)
the user must read the
ITSRCR
Registerto deter-
minethe sourceof theinterrupt,either
IT2
forTx (if
the bit 2 is 1) or
IT3
for Rx (if the bit 3 is 1).
Once the Interrupt has been serviced, the host
mustacknowledgeit by writinga$00valueinto the
register
ITRES2
for
IT2
, or
ITRES3
for
IT3
.
These registers have the followingaddress :
Name
ITRES2
ITRES3
ITMASK
ITSRCR
Address
$42
$43
$4F
$50
Type
Write only
Write only
Read/Write
Read Only
Description
Clear IT2
Clear IT3
Interrupt Mask
Interrupt Source
Notes : 1. TheST75C530/540doesnotcheckthattheinterrupthas
been acknowledged.
2. Even if the Host does not use the interruption, the
ST75C530/540 will set the bit2 (for
IT2
) and/or bit 3 (for
IT3
) of the
ITSRCR
.
3. The ST75C530/540 uses only the Data Buffer Status
Bytes to detectOverrun orUnderrun Error.These errors
are reportedinto the
SYSERR
byte, andcould generate
an interrupt
IT0
.
The equivalentschematicis : see Figure21.
The interrupt mechanism assumes that the Host
processor uses a Level sensitive interrupt (active
low). The Flow chart of the Host interrupt service
routine looksgeneraly like Figure22.
X.5 - Data Format
Different Formats of Data can be Transmitted/Re-
ceived to/from the TelephoneLine.
These Formatscan be selectedwhenentering the
Data Mode by usingthe
FORM
command.
The Format of the Data canbe changed,on the fly
in the DataMode duringthe samecommunication,
bysendingadifferent
FORM
commandat anytime.
Note that for Full Duplex operation the Data For-
mat is the same for the transmitter and the re-
ceiver.
X - PARALLEL DATA EXCHANGE
(continued)
ST75C530- ST75C540
61/84
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