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參數(shù)資料
| 型號(hào)： | ST75C540FP-A |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | SUPER INTEGRATED DEVICESWITH DSP, AFE & MEMORIES FORTELEPHONY,MODEM, FAXOVERINTERNET& POTSLINES |
| 中文描述： | 超級(jí)綜合DEVICESWITH數(shù)字信號(hào)處理器，模擬前端 |
| 文件頁數(shù)： | 22/84頁 |
| 文件大?。?/td> | 599K |
| 代理商： | ST75C540FP-A |
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VI.1.1.7- InterruptControlArea
The interrupt area, that start afterthe address$40
controls the behaviour of the Interrupts mecha-
nism. Register ITSRCR defines the source of the
interrupt,the registerITMASK allows independent
enabling or disabling of any of the interrupt’s
source, registers ITREST0 to ITREST6 reset the
correspondinginterruptsource.
TheseregistersarenotaffectedbyaINITcommand,
theyareonlyresetedbya HardwareRESETsignal.
VI.1.1.8- GeneralIO andRelay Output Area
A set of 5 registers is directly accessible by the
controller to program the General IO pins and
Relay Outputs (see Paragraph VI.1.3 “Host Inter-
face Summary”). Two registers IODIR0 and IO-
DIR1 define the type of the IO pin, either Input or
Output (0 = input, 1 = output), and two registers
IODATA0 and IODATA1 define the IO pin signals.
The fifth register definesthe Relayoutput signals.
TheseregistersarenotaffectedbyaINITcommand,
theyareonlyresetedbya HardwareRESETsignal.
The general IO are setup as input after the power
up or an hardware RESET. The relay output are
open after power up or an hardwareRESET.
VI.1.2- Interruptions
The ST75C530/540 can generate 7 interrupts for
the controller. The interrupt handling is made with
a setof registerslocatedfrom $40 to $5F.
The interruptions generated by the ST75C530/540
come
from several sources. Once the
ST75C530/540raisesan interrupt,a signal(SINTR)
is sent to the controller. The controller has then to
processtheinterruptandclearit.Theinterruptsource
can be examined in the interrupt source register
ITSRCR located a $50. According to the ITSRCR
bits, the interrupt source can be determined. Then
writing a zero at one of the memory location$40 to
$46 (Reset Interrupt Register ITRES[0..6]) will re-
set the corresponding interrupt (and thus acknow-
ledgeit). Thesourceof theinterruptcanbe masked
globally or individually using the Interrupt Mast
register ITMASK located at $4F.
The interrupt sourcesare :
- IT0 : Error
This signifies that an error has occurredand the
error code is available in the error status byte
SYSERR.Thisbytecanbe selectivelyclearedby
the CSE command.
- IT1 : VOCODERBuffer
Each time the ST75C530/540 have coded a
frame (CODER Mode) or decodeda frame(DE-
CODER Mode) this interrupt is generated.
- IT2 : Tx Buffer
Each timethe ST75530/C540freesa databuffer,
this interrupt is generated.
- IT3 : Rx Buffer
Each time the ST75C530/540 has filled a data
buffer,this interrupt is generated.
This signifies that the status byte has changed
and must be checkedby the controller.
- IT5 : Low Power Mode
TheST75C530/540hasbeenawakenedfromthe
low power mode by a low level on the RING pin
or a dummywrite issued by the host.
- IT6 : CommandAcknowledge
This signifies that the ST75C530/540 has read
the last command entered by the host, incre-
mented the command counter COMACK, and is
readyfor a newcommand.
Note : Interruptregisters are cleared after a Hard-
ware RESET. These registers are not affectedby
a
INIT
Command.
VI - USERINTERFACE
(continued)
ST75C530 - ST75C540
22/84
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