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參數(shù)資料
| 型號(hào)： | ST75C530FP-A |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | SUPER INTEGRATED DEVICESWITH DSP, AFE & MEMORIES FORTELEPHONY,MODEM, FAXOVERINTERNET& POTSLINES |
| 中文描述： | 超級(jí)綜合DEVICESWITH數(shù)字信號(hào)處理器，模擬前端 |
| 文件頁數(shù)： | 27/84頁 |
| 文件大?。?/td> | 599K |
| 代理商： | ST75C530FP-A |
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VI.4 - Status - Reports
VI.4.1- Status
TheST75C530/540hasa dedicatedstatusreport-
ing area locatedin its dual port RAM. This allow a
continuousmonitoring of the statusvariableswith-
out interruptingthe ST75C530/540.
The first status byte givesthe error status.Issuing
of an error status can also be flagged by a mask-
able interruptfor the controller.The significationof
the error codes are given in Chapter VIII.
Thesecondand thirdstatusbytesgivethegeneral
status of the modem. These status include for
example the ITU-T circuit status and other items
described in Chapter VIII “STATUS DESCRIP-
TION”. These two status can generate, when a
changeoccurs,an interruptto the controller; each
bit of the two byte word can be masked inde-
pendently.
The forth byte gives in real time a measure of the
receptionquality.Thisinformationmaybeusedbythe
controllertomonitorthequalityofthereceivedbits.
Four other locations are dedicated for custom
status reporting. The controller can program the
ST75C530/540for a realtime monitoring of any of
its internal RAM location. High byte or low byte of
any word can thusbe monitored.
VI.4.2- Reports
The ST75C530/540featuresan acknowledgeand
report facility. The acknowledge of a command is
monitored by a counter COMACK located in the
dualportRAM. Eachtime a commandis readfrom
the command area, the ST75C530/540will incre-
mentthiscounter.Forinstance,whena MR(Mem-
ory Read) command is issued, the data is first
written in the report area, and the counteris incre-
mentedafterwards.Thiswayof processinginsures
dataintegrity and gives additional synchronization
betweenthe controllerand the data pump.
VI.5 - Data Exchanges
The ST75C530/540 accepts many kinds of data
exchange: thedefaultmode usesthesynchronous
parallel exchange. Other modes include HDLC
framingsupportand UART. Detaileddescriptionof
the Data Buffer Exchanges modes is available in
the paragraphX.
VI.5.1- SynchronousParallelMode
The data exchanges are made through the dual
port RAM and arebyte synchronousoriented.The
double bufferfacilities of the ST75C530/540allow
an efficientbufferingof the data.
VI.5.1.1- Transmit
The controller must first fill at least the first buffer
of data(TxBuffer0) withthe bitsto be transmitted.
In order to perform this operation, the controller
must first check the Tx Buffer 0 status word
DTTBS0. If this buffer is empty, the controller fills
the data buffer locations (up to 64 bits), and then
writesinDTTBS0the numberof bytescontainedin
the buffer. The controller can then either proceed
with the second buffer or initiate the transmission
witha XMITcommand.
TheST75C530/540copiesthe contentsofthedata
buffer and then clears the buffer status word in
orderto makeit againavailable,thengeneratesan
IT2interrupt.Thenumber of bytesspecifiedby the
status word is then queued for transmission. The
processgoeson with thetwobuffersuntilan XMIT
command stops the transmission. After the finish-
ingXMIT command has been issued, the lastbuff-
ers are emptiedby the ST75C530/540.
Errorsoccurwhenboth buffersareemptywhilethe
transmit bit queue is also empty.Error is signalled
withan IT0interruptionto the controller.
VI.5.1.2- Receive
Thecontroller shouldtake careof releasingthe Rx
buffers before the Data Carrier Detect goes true.
Thisismadebywritingzeroin theRx BufferStatus
0 and 1. The ST75C530/540 then fills the first
buffer,and oncefilledsetsthe statusword withthe
number of bytes received and then generatesan
IT3 interrupt. It then takes control of the second
buffer and operatesthe same way. The controller
must check the status of the buffers and empty
them. Once the data read, the controller must
releasethe used bufferand wait forthe nextbuffer
to be filled.
Error occurs when both buffers are declared full,
and incoming bits continue to arrive from the line.
Error is signaled by an IT0 interrupt.
VI.5.2- HDLCParallel Mode
Thismode implementspart of the HighLevel Data
Link Control formats and procedures. It is well
suited for error correcting protocols like ECM or
FAXT4/T30recommendations.Itsupportstheflag-
ginggeneration,16-bitFrameCheckSequence,as
well as the Zeroinsertion/deletionmechanism.
VI.5.3- UARTParallel Mode
This mode implement a 7 or 8 bit data format, it is
well suited for Caller ID or Minitel applications.
VI - USERINTERFACE
(continued)
ST75C530- ST75C540
27/84
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| ST75C530PQFP | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication IC |
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