參數(shù)資料
型號： ST72T2311R6T7
廠商： 意法半導(dǎo)體
英文描述： 8-BIT MCU WITH NESTED INTERRUPTS, EEPROM, ADC, 16-BIT TIMERS, 8-BIT PWM ART, SPI, SCI, CAN INTERFACES
中文描述： 8位嵌套中斷，EEPROM存儲器，模數(shù)轉(zhuǎn)換器，16位定時(shí)器，8位PWM藝術(shù)，SPI和脊髓損傷，微控制器的CAN接口
文件頁數(shù)： 87/164頁
文件大小： 1043K
代理商： ST72T2311R6T7
ST72311R, ST72511R, ST72512R, ST72532R
29/164
INTERRUPTS (Cont’d)
Servicing Pending Interrupts
As several interrupts can be pending at the same
time, the interrupt to be taken into account is deter-
mined by the following two-step process:
– the highest software priority interrupt is serviced,
– if several interrupts have the same software pri-
ority then the interrupt with the highest hardware
priority is serviced first.
Figure 15 describes this decision process.
Figure 15. Priority Decision Process
When an interrupt request is not serviced immedi-
ately, it is latched and then processed when its
software priority combined with the hardware pri-
ority becomes the highest one.
Note 1: The hardware priority is exclusive while
the software one is not. This allows the previous
process to succeed with only one interrupt.
Note 2: RESET, TRAP and TLI are non maskable
and they can be considered as having the highest
software priority in the decision process.
Different Interrupt Vector Sources
Two interrupt source types are managed by the
ST7 interrupt controller: the non-maskable type
(RESET, TLI, TRAP) and the maskable type (ex-
ternal or from internal peripherals).
Non-Maskable Sources
These sources are processed regardless of the
state of the I1 and I0 bits of the CC register (see
Figure 14). After stacking the PC, X, A and CC
registers (except for RESET), the corresponding
vector is loaded in the PC register and the I1 and
I0 bits of the CC are set to disable interrupts (level
3). These sources allow the processor to exit
HALT mode.
s
TLI (Top Level Hardware Interrupt)
This hardware interrupt occurs when a specific
edge is detected on the dedicated TLI pin. Its de-
tailed specification is given in the Miscellaneous
register chapter.
s
TRAP (Non Maskable Software Interrupt)
This software interrupt is serviced when the TRAP
instruction is executed. It will be serviced accord-
ing to the flowchart on Figure 14 as a TLI.
s
RESET
The RESET source has the highest priority in the
ST7. This means that the first current routine has
the highest software priority (level 3) and the high-
est hardware priority.
See the RESET chapter for more details.
Maskable Sources
Maskable interrupt vector sources can be serviced
if the corresponding interrupt is enabled and if its
own interrupt software priority (in ISPRx registers)
is higher than the one currently being serviced (I1
and I0 in CC register). If any of these two condi-
tions is false, the interrupt is latched and thus re-
mains pending.
s
External Interrupts
External interrupts allow the processor to exit from
HALT low power mode.
External interrupt sensitivity is software selectable
through the Miscellaneous registers (MISCRx).
External interrupt triggered on edge will be latched
and the interrupt request automatically cleared
upon entering the interrupt service routine.
If several input pins of a group connected to the
same interrupt line are selected simultaneously,
these will be logically ORed.
s
Peripheral Interrupts
Usually the peripheral interrupts cause the MCU to
exit from HALT mode except those mentioned in
the “Interrupt Mapping” table.
A peripheral interrupt occurs when a specific flag
is set in the peripheral status registers and if the
corresponding enable bit is set in the peripheral
control register.
The general sequence for clearing an interrupt is
based on an access to the status register followed
by a read or write to an associated register.
Note: The clearing sequence resets the internal
latch. A pending interrupt (i.e. waiting for being
serviced) will therefore be lost if the clear se-
quence is executed.
PENDING
SOFTWARE
Different
INTE RRUPTS
Same
HIGHES T HARDWARE
PRIORITY SERVICED
PRIORITY
HIGHEST SOFTWAR E
PRIORITY SERVIC ED
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