參數(shù)資料
型號： ST72T2311R6T7
廠商： 意法半導(dǎo)體
英文描述： 8-BIT MCU WITH NESTED INTERRUPTS, EEPROM, ADC, 16-BIT TIMERS, 8-BIT PWM ART, SPI, SCI, CAN INTERFACES
中文描述： 8位嵌套中斷，EEPROM存儲器，模數(shù)轉(zhuǎn)換器，16位定時器，8位PWM藝術(shù)，SPI和脊髓損傷，微控制器的CAN接口
文件頁數(shù)： 101/164頁
文件大?。?/td> 1043K
代理商： ST72T2311R6T7
ST72311R, ST72511R, ST72512R, ST72532R
41/164
I/O PORTS (Cont’d)
CAUTION: The alternate function must not be ac-
tivated as long as the pin is configured as input
with interrupt, in order to avoid generating spurious
interrupts.
Analog alternate function
When the pin is used as an ADC input, the I/O
must be configured as floating input. The analog
multiplexer (controlled by the ADC registers)
switches the analog voltage present on the select-
ed pin to the common analog rail which is connect-
ed to the ADC input.
It is recommended not to change the voltage level
or loading on any port pin while conversion is in
progress. Furthermore it is recommended not to
have clocking pins located close to a selected an-
alog pin.
WARNING: The analog input voltage level must
be within the limits stated in the absolute maxi-
mum ratings.
8.3 I/O PORT IMPLEMENTATION
The hardware implementation on each I/O port de-
pends on the settings in the DDR and OR registers
and specific feature of the I/O port such as ADC In-
put or true open drain.
Switching these I/O ports from one state to anoth-
er should be done in a sequence that prevents un-
wanted side effects. Recommended safe transi-
tions are illustrated in Figure 26 Other transitions
are potentially risky and should be avoided, since
they are likely to present unwanted side-effects
such as spurious interrupt generation.
Figure 26. Interrupt I/O Port State Transitions
The I/O port register configurations are summa-
rized as follows.
Standard Ports
PA5:4, PC7:0, PD7:0, PE7:3, PE1:0, PF7:3
Interrupt Ports
PA2:0, PB7:5, PB2:0, PF1:0 (with pull-up)
PA3, PB4, PB3, PF2 (without pull-up)
True Open Drain Ports
PA7:6
Pull-up Input Port (CANTX requirement)
PE2
01
floating/pull-up
interrupt
INPUT
00
floating
(reset state)
INPUT
10
open-drain
OUTPUT
11
push-pull
OUTPUT
XX
= DDR, OR
MODE
DDR
OR
floating input
0
pull-up input
0
1
open drain output
1
0
push-pull output
1
MODE
DDR
OR
floating input
0
pull-up interrupt input
0
1
open drain output
1
0
push-pull output
1
MODE
DDR
OR
floating input
0
floating interrupt input
0
1
open drain output
1
0
push-pull output
1
MODE
DDR
floating input
0
open drain (high sink ports)
1
MODE
pull-up input
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