參數(shù)資料
型號： ST72T2311R6T7
廠商： 意法半導(dǎo)體
英文描述： 8-BIT MCU WITH NESTED INTERRUPTS, EEPROM, ADC, 16-BIT TIMERS, 8-BIT PWM ART, SPI, SCI, CAN INTERFACES
中文描述： 8位嵌套中斷，EEPROM存儲器，模數(shù)轉(zhuǎn)換器，16位定時器，8位PWM藝術(shù)，SPI和脊髓損傷，微控制器的CAN接口
文件頁數(shù)： 49/164頁
文件大小： 1043K
代理商： ST72T2311R6T7
ST72311R, ST72511R, ST72512R, ST72532R
142/164
EMC CHARACTERISTICS (Cont’d)
12.7.2.2 Static and Dynamic Latch-Up
s
LU: 3 complementary static tests are required
on 10 parts to assess the latch-up performance.
A supply overvoltage (applied to each power
supply pin), a current injection (applied to each
input, output and configurable I/O pin) and a
power supply switch sequence are performed
on each sample. This test conforms to the EIA/
JESD 78 IC latch-up standard. For more details,
refer to the AN1181 ST7 application note.
s
DLU: Electro-Static Discharges (one positive
then one negative test) are applied to each pin
of 3 samples when the micro is running to
assess the latch-up performance in dynamic
mode. Power supplies are set to the typical
values, the oscillator is connected as near as
possible to the pins of the micro and the
component is put in reset mode. This test
conforms to the IEC1000-4-2 and SAEJ1752/3
standards and is described in Figure 76. For
more
details,
refer
to
the
AN1181
ST7
application note.
Electrical Sensitivities
Figure 76. Simplified Diagram of the ESD Generator for DLU
Notes:
1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the JEDEC spec-
ifications, that means when a device belongs to Class A it exceeds the JEDEC standard. B Class strictly covers all the
JEDEC criteria (international standard).
2. Schaffner NSG435 with a pointed test finger.
Symbol
Parameter
Conditions
Class 1)
LU
Static latch-up class
TA=+25°C
TA=+85°C
A
DLU
Dynamic latch-up class
VDD=5.5V, fOSC=4MHz, TA=+25°C
TBD
RCH=50M
RD=330
CS=150pF
ESD
HV RELAY
DISCHAR GE TIP
DISCHARGE
RETURN CONNECTION
GENERATOR 2)
ST7
VDD
VSS
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