參數(shù)資料
型號(hào): ST72P63BH4T1
廠商: STMICROELECTRONICS
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PQFP48
封裝: 7 X 7 MM, ROHS COMPLIANT, LQFP-48
文件頁數(shù): 71/145頁
文件大?。?/td> 2984K
代理商: ST72P63BH4T1
ST7263BDx ST7263BHx ST7263BKx ST7263BE
31/145
Power saving modes (Cont’d)
9.3 Slow mode
In Slow mode, the oscillator frequency can be di-
vided by 2 as selected by the SMS bit in the Mis-
cellaneous Register. The CPU and peripherals are
clocked at this lower frequency. Slow mode is
used to reduce power consumption, and enables
the user to adapt the clock frequency to the avail-
able supply voltage.
9.4 Wait mode
Wait mode places the MCU in a low power con-
sumption mode by stopping the CPU.
This power saving mode is selected by calling the
“WFI” ST7 software instruction.
All peripherals remain active. During Wait mode,
the I bit of the CC register is forced to 0 to enable
all interrupts. All other registers and memory re-
main unchanged. The MCU remains in Wait mode
until an interrupt or Reset occurs, whereupon the
Program Counter branches to the starting address
of the interrupt or Reset service routine.
The MCU will remain in Wait mode until a Reset or
an Interrupt occurs, causing it to wake up.
Refer to Figure 21.
Related documentation
AN 980: ST7 Keypad Decoding Techniques, Im-
plementing Wake-Up on Keystroke
AN1014: How to Minimize the ST7 Power Con-
sumption
AN1605: Using an active RC to wakeup the
ST7LITE0 from power saving mode
Figure 21. Wait mode flowchart
WFI INSTRUCTION
RESET
INTERRUPT
Y
N
Y
CPU CLOCK
OSCILLATOR
PERIPH. CLOCK
I-BIT
ON
CLEARED
OFF
CPU CLOCK
OSCILLATOR
PERIPH. CLOCK
I-BIT
ON
SET
ON
FETCH RESET VECTOR
OR SERVICE INTERRUPT
4096 CPU CLOCK
CYCLES DELAY
IF RESET
Note: Before servicing an interrupt, the CC register is
pushed on the stack. The I-Bit is set during the inter-
rupt routine and cleared when the CC register is
popped.
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