參數(shù)資料
型號(hào)： ST72P63BH4T1
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PQFP48
封裝： 7 X 7 MM, ROHS COMPLIANT, LQFP-48
文件頁數(shù)： 70/145頁
文件大?。?/td> 2984K
代理商： ST72P63BH4T1
ST7263BDx ST7263BHx ST7263BKx ST7263BE
30/145
9 Power saving modes
9.1 Introduction
To give a large measure of flexibility to the applica-
tion in terms of power consumption, two main pow-
er saving modes are implemented in the ST7.
After a RESET, the normal operating mode is se-
lected by default (Run mode). This mode drives
the device (CPU and embedded peripherals) by
means of a master clock which is based on the
main oscillator frequency divided by 3 (fCPU).
From Run mode, the different power saving
modes may be selected by setting the relevant
register bits or by calling the specific ST7 software
instruction whose action depends on the oscillator
status.
9.2 Halt mode
The MCU consumes the least amount of power in
Halt mode. The Halt mode is entered by executing
the HALT instruction. The internal oscillator is then
turned off, causing all internal processing to be
stopped, including the operation of the on-chip pe-
ripherals.
When entering Halt mode, the I bit in the Condition
Code Register is cleared. Thus, all external inter-
rupts (ITi or USB end suspend mode) are allowed
and if an interrupt occurs, the CPU clock becomes
active.
The MCU can exit Halt mode on reception of either
an external interrupt on ITi, an end suspend mode
interrupt coming from USB peripheral, or a reset.
The oscillator is then turned on and a stabilization
time is provided before releasing CPU operation.
The stabilization time is 4096 CPU clock cycles.
After the start up delay, the CPU continues opera-
tion by servicing the interrupt which wakes it up or
by fetching the reset vector if a reset wakes it up.
Figure 20. Halt mode flowchart
N
EXTERNAL
INTERRUPT*
RESET
HALT INSTRUCTION
4096 CPU CLOCK
FETCH RESET VECTOR
OR SERVICE INTERRUPT
CYCLES DELAY
CPU CLOCK
OSCILLATOR
PERIPH. CLOCK
I-BIT
ON
SET
ON
CPU CLOCK
OSCILLATOR
PERIPH. CLOCK
I-BIT
OFF
CLEARED
OFF
Y
Note: Before servicing an interrupt, the CC register is
pushed on the stack. The I-Bit is set during the inter-
rupt routine and cleared when the CC register is
popped.
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