參數資料
型號: ST72P63BH4T1
廠商: STMICROELECTRONICS
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PQFP48
封裝: 7 X 7 MM, ROHS COMPLIANT, LQFP-48
文件頁數: 32/145頁
文件大?。?/td> 2984K
代理商: ST72P63BH4T1
ST7263BDx ST7263BHx ST7263BKx ST7263BE
127/145
8-bit ADC characteristics (Cont’d)
ADC accuracy with VDD=5V, fCPU=8 MHz, fADC=4 MHz RAIN< 10k
Notes:
1. ADC Accuracy vs. Negative Injection Current:
For IINJ-=0.8mA, the typical leakage induced inside the die is 1.6A and the effect on the ADC accuracy is a loss of 1 LSB
for each 10K
increase of the external analog source impedance. This effect on the ADC accuracy has been observed
under worst-case conditions for injection:
- negative injection
- injection to an Input with analog capability, adjacent to the enabled Analog Input
- at 5V VDD supply, and worst case temperature.
2. Data based on characterization results over the whole temperature range, not tested in production.
3. Data based on characterization results, to guarantee 99.73% within ± max value from 0°C to 70°C ( ± 3
σ distribution
limits).
Figure 75. ADC accuracy characteristics
Symbol
Parameter
Typ
Max 2) 3)
|ET|
Total unadjusted error 1)
1.5
2
|EO|
Offset error 1)
0.5
1
|EG|
Gain Error 1)
0.5
1.5
|ED|
Differential linearity error 1)
11.5
|EL|
Integral linearity error 1)
11.5
EO
EG
1LSBIDEAL
1LSB
IDEAL
V
DDA
V
SSA
256
-----------------------------------------
=
Vin (LSBIDEAL)
(1) Example of an actual transfer curve
(2) The ideal transfer curve
(3) End point correlation line
ET=Total Unadjusted Error: maximum deviation
between the actual and the ideal transfer curves.
EO=Offset Error: deviation between the first actual
transition and the first ideal one.
EG=Gain Error: deviation between the last ideal
transition and the last actual one.
ED=Differential Linearity Error: maximum deviation
between actual steps and the ideal one.
EL=Integral Linearity Error: maximum deviation
between any actual transition and the end point
correlation line.
Digital Result ADCDR
255
254
253
5
4
3
2
1
0
7
6
1
234
567
253 254 255 256
(1)
(2)
ET
ED
EL
(3)
VDDA
VSSA
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