參數(shù)資料
型號: ST72F611F1B1
英文描述: 64Mb EDO/FPM - OBSOLETE
中文描述: ST7的-低速USB 8 - 3端點位MCU。閃存。內(nèi)徑。水分散粒劑。定時器
文件頁數(shù): 82/161頁
文件大?。?/td> 2070K
代理商: ST72F611F1B1
ST72324
27/161
6.4 SYSTEM INTEGRITY MANAGEMENT (SI)
The System Integrity Management block contains
the Low Voltage Detector (LVD), Auxiliary Voltage
Detector (AVD) functions and Clock Security Sys-
tem (CSS). It is managed by the SICSR register.
6.4.1 Low Voltage Detector (LVD)
The Low Voltage Detector function (LVD) gener-
ates a static reset when the VDD supply voltage is
below a VIT- reference value. This means that it
secures the power-up as well as the power-down
keeping the ST7 in reset.
The VIT- reference value for a voltage drop is lower
than the VIT+ reference value for power-on in order
to avoid a parasitic reset when the MCU starts run-
ning and sinks current on the supply (hysteresis).
The LVD Reset circuitry generates a reset when
VDD is below:
–VIT+ when VDD is rising
–VIT- when VDD is falling
The LVD function is illustrated in Figure 15.
The voltage threshold can be configured by option
byte to be low, medium or high.
Provided the minimum VDD value (guaranteed for
the oscillator frequency) is above VIT-, the MCU
can only be in two modes:
– under full software control
– in static safe reset
In these conditions, secure operation is always en-
sured for the application without the need for ex-
ternal reset hardware.
During a Low Voltage Detector Reset, the RESET
pin is held low, thus permitting the MCU to reset
other devices.
Notes:
The LVD allows the device to be used without any
external RESET circuitry.
If the medium or low thresholds are selected, the
detection may occur outside the specified operat-
ing voltage range. Below 3.8V, device operation is
not guaranteed.
The LVD is an optional function which can be se-
lected by option byte.
Figure 15. Low Voltage Detector vs Reset
VDD
VIT+
RESET
VIT-
Vhys
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