參數(shù)資料
型號： ST72F611F1B1
英文描述： 64Mb EDO/FPM - OBSOLETE
中文描述： ST7的-低速USB 8 - 3端點位MCU。閃存。內(nèi)徑。水分散粒劑。定時器
文件頁數(shù)： 109/161頁
文件大小： 2070K
代理商： ST72F611F1B1
ST72324
51/161
10 ON-CHIP PERIPHERALS
10.1 WATCHDOG TIMER (WDG)
10.1.1 Introduction
The Watchdog timer is used to detect the occur-
rence of a software fault, usually generated by ex-
ternal interference or by unforeseen logical condi-
tions, which causes the application program to
abandon its normal sequence. The Watchdog cir-
cuit generates an MCU reset on expiry of a pro-
grammed time period, unless the program refresh-
es the counter’s contents before the T6 bit be-
comes cleared.
10.1.2 Main Features
s
Programmable free-running downcounter
s
Programmable reset
s
Reset (if watchdog activated) when the T6 bit
reaches zero
s
Optional
reset
on
HALT
instruction
(configurable by option byte)
s
Hardware Watchdog selectable by option byte
10.1.3 Functional Description
The counter value stored in the Watchdog Control
register (WDGCR bits T[6:0]), is decremented
every 16384 fOSC2 cycles (approx.), and the
length of the timeout period can be programmed
by the user in 64 increments.
If the watchdog is activated (the WDGA bit is set)
and when the 7-bit timer (bits T[6:0]) rolls over
from 40h to 3Fh (T6 becomes cleared), it initiates
a reset cycle pulling low the reset pin for typically
500ns.
The application
program must write in the
WDGCR register at regular intervals during normal
operation to prevent an MCU reset. This down-
counter is free-running: it counts down even if the
watchdog is disabled. The value to be stored in the
WDGCR register must be between FFh and C0h:
– The WDGA bit is set (watchdog enabled)
– The T6 bit is set to prevent generating an imme-
diate reset
– The T[5:0] bits contain the number of increments
which represents the time delay before the
watchdog produces a reset (see Figure 33. Ap-
proximate Timeout Duration). The timing varies
between a minimum and a maximum value due
to the unknown status of the prescaler when writ-
ing to the WDGCR register (see Figure 34).
Following a reset, the watchdog is disabled. Once
activated it cannot be disabled, except by a reset.
The T6 bit can be used to generate a software re-
set (the WDGA bit is set and the T6 bit is cleared).
If the watchdog is activated, the HALT instruction
will generate a Reset.
Figure 32. Watchdog Block Diagram
RESET
WDGA
6-BIT DOWNCOUNTER (CNT)
fOSC2
T6
T0
WDG PRESCALER
WATCHDOG CONTROL REGISTER (WDGCR)
DIV 4
T1
T2
T3
T4
T5
12-BIT MCC
RTC COUNTER
MSB
LSB
DIV 64
0
5
6
11
MCC/RTC
TB[1:0] bits
(MCCSR
Register)
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