參數(shù)資料
型號： ST72F611F1B1
英文描述： 64Mb EDO/FPM - OBSOLETE
中文描述： ST7的-低速USB 8 - 3端點(diǎn)位MCU。閃存。內(nèi)徑。水分散粒劑。定時(shí)器
文件頁數(shù)： 131/161頁
文件大?。?/td> 2070K
代理商： ST72F611F1B1
ST72324
71/161
16-BIT TIMER (Cont’d)
10.3.4 Low Power Modes
10.3.5 Interrupts
Note: The 16-bit Timer interrupt events are connected to the same interrupt vector (see Interrupts chap-
ter). These events generate an interrupt if the corresponding Enable Control Bit is set and the interrupt
mask in the CC register is reset (RIM instruction).
* The ICF2 and OCF2 bits are forced by hardware to 0 in Timer A, hence there is no interrupt event for
these flags.
10.3.6 Summary of Timer modes
2) See note 5 and 6 in Section 10.3.3.5 One Pulse Mode
4) The TAOC2HR, TAOC2LR registers are write only in Timer A. Output Compare 2 event cannot be gen-
erated, OCF2 is forced by hardware to 0.
5) Input Capture 2 is not implemented in Timer A. ICF2 bit is forced by hardware to 0.
Mode
Description
WAIT
No effect on 16-bit Timer.
Timer interrupts cause the device to exit from WAIT mode.
HALT
16-bit Timer registers are frozen.
In HALT mode, the counter stops counting until Halt mode is exited. Counting resumes from the previous
count when the MCU is woken up by an interrupt with “exit from HALT mode” capability or from the counter
reset value when the MCU is woken up by a RESET.
If an input capture event occurs on the ICAP
i pin, the input capture detection circuitry is armed. Consequent-
ly, when the MCU is woken up by an interrupt with “exit from HALT mode” capability, the ICF
i bit is set, and
the counter value present when exiting from HALT mode is captured into the IC
iR register.
Interrupt Event
Event
Flag
Enable
Control
Bit
Exit
from
Wait
Exit
from
Halt
Input Capture 1 event/Counter reset in PWM mode
ICF1
ICIE
Yes
No
Input Capture 2 event
ICF2
*
Yes
No
Output Compare 1 event (not available in PWM mode)
OCF1
OCIE
Yes
No
Output Compare 2 event (not available in PWM mode)
OCF2
*
Yes
No
Timer Overflow event
TOF
TOIE
Yes
No
MODES
TIMER RESOURCES
Input Capture 1
Input Capture 2
Output Compare 1 Output Compare 2
Input Capture (1 and/or 2)
Yes
Yes2)5)
Yes
Yes4)
Output Compare (1 and/or 2)
Yes
Yes5)
Yes
Yes4)
One Pulse Mode
No
Not
Recommended1)5)
No
Partially 2)
PWM Mode
No
Not
Recommended3)5)
No
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